Showing papers on "State (computer science) published in 2001"

Electrically alterable non-volatile memory with N-bits per cell

Abstract: An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell is conducted by applying a plurality of programming signals having different characteristics to the cell. The programming signals include at least a first programming signal which programs the cell by a first increment and a subsequent programming signal which programs the cell by a second increment smaller than the first increment. As the cell is being programmed to a selected state, its programming status is verified independently of reference values bounding the memory states. For this purpose, a signal indicative of the programming status (e.g., the cell's bit line signal) is compared with a reference signal corresponding to the selected state but having a value different from the reference value or values bounding the selected state. The programming operation can thus be controlled without actually reading the memory state of the cell.

Reporting the state of an apparatus to a remote computer

Abstract: The state of an apparatus is reported to a remote computer using an embedded device in the apparatus. The embedded device detects the state, generates a message that reports the state using a self-describing computer language, and sends the message to the remote computer. The remote computer receives the message and extracts the state of the embedded device from the message.

Progress on the State Explosion Problem in Model Checking

Abstract: Model checking is an automatic verification technique for finite state concurrent systems. In this approach to verification, temporal logic specifications are checked by an exhaustive search of the state space of the concurrent system. Since the size of the state space grows exponentially with the number of processes, model checking techniques based on explicit state enumeration can only handle relatively small examples. This phenomenon is commonly called the "State Explosion Problem". Over the past ten years considerable progress has been made on this problem by (1) representing the state space symbolically using BDDs and by (2) using abstraction to reduce the size of the state space that must be searched. As a result model checking has been used successfully to find extremely subtle errors in hardware controllers and communication protocols. In spite of these successes, however, additional research is needed to handle large designs of industrial complexity. This aim of this paper is to give a succinct survey of symbolic model checking and to introduce the reader to recent advances in abstraction.

Method of correcting a machine check error

Abstract: Processor implementation-specific instructions save a processor state in a system memory and attempt to correct the error. Control is then transferred to processor-independent instructions. Control is returned to the processor implementation-specific instructions which then return to an interrupted context of the processor by restoring the processor state.

Tamper resistant microprocessor

Abstract: Under a multi-task environment, a tamper resistant microprocessor saves a context information for one program whose execution is to be interrupted, where the context information contains information indicating an execution state of that one program and the execution code encryption key of that one program. An execution of that one program can be restarted by recovering the execution state of that one program from the saved context information. The context information can be encrypted by using the public key of the microprocessor, and then decrypted by using the secret key of the microprocessor.

Techniques for the creation of digital watermarks in sequential circuit designs

Abstract: We present a methodology for the watermarking of synchronous sequential circuits that makes it possible to identify the authorship of designs by imposing a digital watermark on the state transition graph (STG) of the circuit. The methodology is applicable to sequential designs that are made available as firm intellectual property, the designation commonly used to characterize designs specified as structural hardware description languages or circuit netlists. The watermarking is obtained by manipulating the STG of the design in such a way as to make it exhibit a chosen property that is extremely rare in nonwatermarked circuits while, at the same time, not changing the functionality of the circuit. This manipulation is performed without ever actually computing this graph in either implicit or explicit form. Instead, the digital watermark is obtained by direct manipulation of the circuit description. We present evidence that no known algorithms for circuit manipulation can be used to efficiently remove or change the watermark and that the process is immune to a variety of other attacks. We present both theoretical and experimental results that show that the watermarking can be created and verified efficiently. We also test possible attack strategies and verify that they are inapplicable to realistic designs of medium to large complexity.

Computerized gaming system, method and apparatus

Abstract: The present invention in various embodiments provides a computerized wagering game method and apparatus that features an operating system kernel, a system handler application that loads and executes gaming program shared objects and features nonvolatile storage that facilitates sharing of information between gaming program objects. The system handler of some embodiments further provides an API library of functions callable from the gaming program objects, and facilitates the use of callback functions on change of data stored in nonvolatile storage. The nonvolatile storage also provides a nonvolatile record of the state of the computerized wagering game, providing protection against loss of the game state due to power loss. The system handler application in various embodiments includes a plurality of device handlers, providing an interface to selected hardware and the ability to monitor hardware-related events.

System and method for computer analysis of computer generated communications to produce indications and warning of dangerous behavior

Abstract: The present invention is a system and method for computer analysis of computer generated communications to produce indications and warnings of dangerous behavior A method of computer analysis of computer generated communications in accordance with the invention, includes collecting at least one computer generated communication produced by or received by an author; parsing the collected at least one computer generated communication to identify categories of information therein; processing the categories of information with at least one analysis to quantify at least one type of information in each category; and generating an output communication when a difference between the quantification of at least one type of information for at least one category and a reference for the at least one category is detected involving a psychological state of the author to which a responsive action should be taken with content of the output communication and the at least one category being programmable to define a psychological state in response to which an action should be taken and what the action is to be taken in response to the defined psychological state

CPU utilization measurement techniques for use in power management

Abstract: A computer system that has multiple performance states periodically obtains utilization information for a plurality of tasks operating on the processor and determines processor utilization according to the utilization information for the plurality of tasks. The system compares the processor utilization to at least one threshold and selectively adjusts a current processor performance state to another performance state according to the comparison.

Memory bus termination with memory unit having termination control

Abstract: Methods and apparatus for a memory system using line termination circuits in each memory unit (e.g., integrated circuit memory device) are disclosed. The memory unit contains termination control logic that sets the state of a controllable termination circuit to control reflections on the data bus. The termination control logic determines the proper state for the termination circuit from the state of its memory unit, and in some cases, from the approximate state of the data bus as gleaned from commands decoded from the command/address bus. A termination configuration register on the unit can be used to define the appropriate termination state for each unit state and/or data bus state.

Method, system, and program for providing data updates to a page including multiple regions of dynamic content

Abstract: Disclosed is a method, system, and program for providing data updates to a page, wherein the page includes multiple regions of dynamic content that may be separately updated independently of each other. The regions of the page are displayed within a presentation program executing on a client. A server transfers the page to the client over a network. The server detects state changes and queues information on the state changes. The server further generates an update package including content indicating the state changes and sends the update package to the client. The presentation program in the client renders the information on the state changes to the regions of the page including the dynamic content modified by the content indicating the state changes.

Method and apparatus for displaying information regarding stored data in a gaming system

Abstract: A gaming system includes a hard disk drive for storing applications and other data. The hard disk drive has multiple storage areas for storing different types of data. Each application executed on the gaming system has an associated data storage area and is prevented from using data storage areas associated with other applications. When saving a game, the saved game data may include a descriptive name of the saved game, a graphic representation of the state of the game when the game was saved, a description of the game state when the game was saved, and a date and time that the game was saved.

Automated power management system for a network of computers

Abstract: A computer system comprising a plurality of computing entities includes automatic power management logic that automatically transitions the system to a state in which less power is consumed when appropriate. The determination as to when this transition should occur is based on determining when demand for the processing abilities of the system are reduced. Once the decision has been made to transition to a reduced power state, the system's power management logic makes this transition in such a way to preferably minimize or at least reduce the performance impact on the system. Also, rather than altering the power state of one of the computing entities in the system, the entity can be deployed as part of another computing system.

Workflow management method and workflow management system of controlling workflow process

Abstract: A workflow management system has synchronousness information, which can be set by a process definition tool in a process definition, for specifying a processing mode for calling a state transition request application programming interface (API). The synchronousness is controlled using a state transition request synchronous process program and a state transition request asynchronous process program. The synchronous process program processes a state transition in a synchronous processing mode in which the state transition is processed from receipt of an inputted state transition request to return of a response. The asynchronous process program processes a state transition in an asynchronous processing mode in which a state transition for a process instance is processed after an inputted state transition request is received and a response is returned. The synchronousness information is referenced to determine whether a state transition is processed in the synchronous or asynchronous processing mode.

Configuration bus interface circuit for FPGAs

Abstract: A bus interface circuit for a programmable logic device (PLD) including an interface multiplexer connected between two or more external communication circuits and a configuration memory array. The interface multiplexer coordinates communication between a selected one of the external communication circuits and a packet processor. The packet processor interprets command/data information transmitted in a bit stream from the selected external communication circuit. In a default state, the interface multiplexer connects dual-purpose input/output pins of the PLD to the packet processor. In an alternative state, the interface multiplexer connects a JTAG interface circuit to the packet processor to facilitate configuration operations through the JTAG pins of the PLD.

An Effective Characterization of Computability in Anonymous Networks

Abstract: We provide effective (i.e., recursive) characterizations of the relations that can be computed on networks where all processors use the same algorithm, start from the same state, and know at least a bound on the network size. Three activation models are considered (synchronous, asynchronous, interleaved).

Method and system for proactively reducing the outage time of a computer system

Abstract: A method (and system) of reducing a time for a computer system to recover from a degradation of performance in a hardware or a software in at least one first node of the computer system, includes monitoring a state of the at least one first node, and based on the monitoring, transferring a state of the at least one first node to a second node prior to the degradation in performance of the hardware or the software of the at least one first node.

Computer processing and programming method using autonomous data handlers

Abstract: A computer processing and programming method calls for creating a plurality of software entities (“molecules”) which can be dynamically configured to process data autonomously. The molecules can send and receive signals indicating the state of a molecule, whether or not a processing task is fulfilled, the results of a processing task, and whether or not the operation of a molecule is to be terminated, interrupted, reconfigured, or continued by creation of one or more “next” molecules. The molecules are created from a common set of software micro-components, which may be programmed in any programming languages to run in any operating system environments. The molecules may reside with a single computing resource, however, they are ideally suited to be deployed with distributed computing resources of different types on a network or in a parallel processing environment. An overall data processing task is performed by creating molecules in a “logic web” which can dynamically adapt to fulfill the task. Logic webs can be assigned to operate with different legacy systems, with applications programmed in different languages, and with data of any type stored in any format. As a result, data processing tasks in distributed or parallel processing environments can be performed much more efficiently, and entirely new types of data processing tasks can be undertaken.

Semiconductor memory device and memory system

Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.

Capturing snapshots of a debuggee's state during a debug session

Abstract: Methods, systems and computer program products are provided for capturing snapshots of a debuggee's state during a debug session. More particularly, this invention relates to capturing state and debug data of a debuggee at intervals during a debug session and allowing a software developer to view and/or annotate the captured state and debug data in a developer preferred manner.

Telecommunications portal capable of interpreting messages from an external device

Abstract: The present invention relates to methods and system for providing telecommunications services, such as call waiting, three-way call, and automatic recall, utilizing a plurality of state machines. Logic specifications define a set of states for each state machine. Each state in turn defines at least one action to be performed in response to a signal received by the state machine. The logic specification for each state machine can be stored, for example, in a textual format in a mark up language, such as HTML, XML, or or other markup language. A compiled representation of the logic specification is generated. Further, a context object tracks a current state of the telecommunication service. The context object accesses the compiled representation in response to an event, e.g., a call progress event, in order to effect a state transition and/or perform an action with respect to the telecommunication service.

Computing with Words

Abstract: From the Publisher: Fuzzy logic refers to a computer’s ability to make decisions involving "grey" or "fuzzy" areas. As linguistics contains numerous "grey" areas, computing with words through the use of fuzzy logic is an extremely hot topic in database and Internet research. This book explores the state of the art in linguistic computation, discussing how current research findings are extending the application of fuzzy logic beyond control engineering and intelligent systems into the use of language on a computer. Fuzzy logic pioneer, Dr. Lofti Zadeh, provides the introduction for this thought-provoking work.

Memory controller supporting redundant synchronous memories

Abstract: A reliable fault-tolerant I/O controller supporting redundant synchronous memories is described. The I/O controller includes multiple I/O control logic units where each I/O control logic unit is in communication with a host server and external peripheral devices. Each I/O control logic unit includes a processor, a memory, and a memory controller. A master I/O control logic unit services I/O transactions from the host server and the external peripheral devices. A slave I/O control logic unit operates in a quiescent state until the master I/O control logic unit experiences a memory failure. At such time, the slave I/O control logic unit resumes operation of the I/O controller. In order to facilitate the switchover from the master I/O control logic unit to the slave I/O control logic unit, the master memory controller performs concurrent memory write operations in both the master and slave memories. The concurrent memory write operations ensure that the memories in both I/O control logic units are in a consistent state in order for the switchover to occur without loss of data.

Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system

Abstract: The present invention relates generally to a protocol engine for use in a multiprocessor computer system. The protocol engine, which implements a cache coherence protocol, includes a clock signal generator for generating signals denoting interleaved even clock periods and odd clock periods, a memory transaction state array for storing entries, each denoting the state of a respective memory transaction, and processing logic. The memory transactions are divided into even and odd transactions whose states are stored in distinct sets of entries in the memory transaction state array. The processing logic has interleaving circuitry for processing during even clock periods the even memory transactions and for processing during odd clock periods the odd memory transactions.

Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools

Abstract: List of Figures. List of Tables. Acknowledgments. 1. Introduction. 2. Background. 3. Burst-Mode Synthesis Path Walk-Through. 4. CHASM: Optimal State Assignment for Asynchronous FSM's. 5. Optimist: Optimal State Minimization for Synchronous FSM's. 6. Optimisto-Synchronous State Minimization for Optimum Output Logic. 7. Optimista: Asynchronous State Minimization for Optimum Output Logic. 8. Minimalist: An Extensible Toolkit for Burst-Mode Synthesis. 9. Conclusions. Appendices. Index.

Method and apparatus for system state monitoring using pattern recognition and neural networks

Abstract: Pattern recognition of common modes by neural networks and other techniques are used to monitor and determine or predict the state of networks, computers, software systems, logical networks or other components of an information system, to report actual or predicted states, and to report other state characteristics.

Programming automation by demonstration

Abstract: A system for programming automation by demonstration where a control program may be created or modified through the process of demonstrating desired behavior using graphical representations (or widgets) of physical, programming, and user interface elements. Widgets have state, or properties, and may also have inherent events associated with them or indirect events that are generated through the demonstration process. The general process of demonstration consists of providing several individual example behaviors. Complete behavior, and thus the resultant code, is generated through inferencing from a number of individual example behaviors. The process of programming automation by demonstration reduces the complexity of the programming task and thereby greatly simplifies the workload of the control programmer, allowing the programmer to concentrate more on the specific automation application at hand rather than on the particulars of the programming language or tools. The invention may be applied to a wide range of automation applications, from home and building automation to industrial automation, and may be practiced by novice and expert-level users.

Verifying CTL properties of infinite state systems by specializing constraint logic programs

Abstract: The goal of automated veri ation of systems is the de nition and the implementation of logi al frameworks whi h allow one: (i) to formally spe ify these systems, and (ii) to prove their properties in an automati way. These logi al frameworks require formalisms both for the des ription of the systems and the des ription of their properties. In this paper we assume that a system makes transitions from states to states and the evolution of a system an be formalized using a omputation tree, whi h is de ned as follows. Given a system S and its initial state s 0 , the root of the omputation tree for S is s 0 , and every node s i of the omputation tree for S has a hild node s j i there exists in S a transition from state s i to state s j . The state s j is alled a su essor state of s i . We assume that in every system for every state s i there exists at least one su essor state. Noti e that the set of all states of a system may be nite or in nite. We also assume that the des ription of the properties of any system an be done in the Computation Tree Logi formalism [4℄ (CTL for short). CTL formulas des ribe properties of omputation trees, and they are built using: (i) atomi state properties, (ii) logi al onne tives: :;^;_, (iii) quanti ers over paths: A (`for all paths') and E (`for some path'), and (iv) quanti ers along paths: G (`for all states on the path'), F (`for some state on the path'). CTL formulas are very expressive, and in parti ular, one may use them to des ribe the so alled safety and liveness properties. Given a CTL formula ' and state s, the semanti s of CTL de nes the satisfa tion relation s j= ' whi h holds whenever ' is true in s [4℄. In this paper we will present a method for verifying CTL properties of possibly in nite state systems by using Constraint Logi Programming [7℄ (CLP, for short) and Program Spe ialization. Our method is appli able to a large lass of on urrent systems, like those des ribed by [14℄.