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Showing papers on "State (computer science) published in 2007"


Book ChapterDOI
03 Sep 2007
TL;DR: This work proposes a combined system which marries rely/guarantee logic and separation logic, and demonstrates the advantages of the combined approach by verifying a lock-coupling list algorithm, which actually disposes/frees removed nodes.
Abstract: In the quest for tractable methods for reasoning about concurrent algorithms both rely/guarantee logic and separation logic have made great advances. They both seek to tame, or control, the complexity of concurrent interactions, but neither is the ultimate approach. Relyguarantee copes naturally with interference, but its specifications are complex because they describe the entire state. Conversely separation logic has difficulty dealing with interference, but its specifications are simpler because they describe only the relevant state that the program accesses. We propose a combined system which marries the two approaches. We can describe interference naturally (using a relation as in rely/guarantee), and where there is no interference, we can reason locally (as in separation logic). We demonstrate the advantages of the combined approach by verifying a lock-coupling list algorithm, which actually disposes/frees removed nodes.

320 citations


Journal ArticleDOI
TL;DR: A stored or transmitted bit's state can deteriorate quite badly before a processing device will be mistaken in deciding which of the two possible values is the original.
Abstract: Digital technology works so well because at the heart of digital representation, there are only a few basic components. Nowadays, these basic components usually are binary digits, bits for short, called binary because they are designed to stand for only two different values, conveniently called zero and one. A stored or transmitted bit's state can deteriorate quite badly before a processing device will be mistaken in deciding which of the two possible values is the original.

201 citations


Patent
03 Apr 2007
TL;DR: In this paper, a building control system is provided that receives information from devices of different subsystems, and a trigger causes a zone controller to store the information in a database, which is used to generate customized reports based on sequences or sets of related events.
Abstract: A building control system is provided that receives information from devices of different subsystems. A trigger causes a zone controller to store the information in a database. The stored data is used to generate customized reports based on sequences or sets of related events. The information from multiple subsystems is consolidated, analyzed, and patterns of behavior are determined. The trigger also causes execution of control actions throughout the building spanning the multiple subsystems, devices, and areas based on the information. An access control subsystem and a non-access control subsystem of the building control system are linked using a common network such that a change in the state of an access control device can affect the state of a non-access control device and a change in the state of a non-access control device can affect the state of an access control device.

186 citations


Journal ArticleDOI
11 Jun 2007
TL;DR: Several remaining challenges in how to specify sequential programs in object-oriented languages such as Java and C# are described and approaches to their solution are described.
Abstract: The state of knowledge in how to specify sequential programs in object-oriented languages such as Java and C# and the state of the art in automated verification tools for such programs have made measurable progress in the last several years. This paper describes several remaining challenges and approaches to their solution.

147 citations


Patent
Daniel Hiltgen1, Rene W. Schmidt1
19 Dec 2007
TL;DR: In this paper, the authors present a method comprising of accessing units of network storage that encode state data of respective virtual machines, wherein the state data for respective ones of the virtual machines are stored in distinct ones of each of the network storage units such that the data for more than one virtual machine are not commingled in any one network storage unit.
Abstract: Some embodiments of the present invention include a method comprising: accessing units of network storage that encode state data of respective virtual machines, wherein the state data for respective ones of the virtual machines are stored in distinct ones of the network storage units such that the state data for more than one virtual machine are not commingled in any one of the network storage units.

131 citations


Patent
Daniel Hiltgen1, Rene W. Schmidt1
19 Dec 2007
TL;DR: In this paper, the authors present a method comprising of representing at least state data of a virtual machine in a unit of network storage of a network storage system and employing data manipulation functionality of the network storage systems to implement a VM operation that manipulates at least the state data.
Abstract: One embodiment of the present invention includes a method comprising: (a) representing at least state data of a virtual machine in a unit of network storage of a network storage system; and (b) employing data manipulation functionality of the network storage system to implement a virtual machine operation that manipulates at least the state data of the virtual machine.

104 citations


Patent
05 Jan 2007
TL;DR: In this paper, a memory device and a method of reading the same includes a phase change element having a data state associated therewith that features maintaining the consistency of the data state of the phase change elements in the presence of a read current.
Abstract: A memory device and a method of reading the same includes a phase change element having a data state associated therewith that features maintaining the consistency of the data state of the phase change element in the presence of a read current. The memory circuit includes a sense amplifier that defines a sensing node. Circuitry selectively places the bit line in data communication with the sensing node, defining a selected bit line. A current source produces a read current, and a switch selectively applies the read current to the sensing node. Logic is in electrical communication with the sensing node to control the total energy to which the phase change material is subjected in the presence of the read current so that the data state remains consistent.

99 citations


Book ChapterDOI
10 Sep 2007
TL;DR: It is shown that the routing imbalances can be used to detect the value of the mask bit, and that this conclusion also holds for masked pre-charged logic styles and for all practical implementations of masked dual-rail logic styles.
Abstract: Masked logic styles use a random mask bit to de-correlate the power consumption of the circuit from the state of the algorithm. The effect of the random mask bit is that the circuit switches between two complementary states with a different power profile. Earlier work has shown that the mask-bit value can be estimated from the power consumption profile, and that masked logic remains susceptible to classic power attacks after only a simple filtering operation. In this contribution we will show that this conclusion also holds for masked pre-charged logic styles and for all practical implementations of masked dual-rail logic styles. Up to now, it was believed that masking and dual-rail can be combined to provide a routing-insensitive logic style. We will show that this assumption is not correct. We demonstrate that the routing imbalances can be used to detect the value of the mask bit. Simulations as well as analysis of design data from an AES chip support this conclusion.

96 citations


Patent
26 Dec 2007
TL;DR: In this paper, a method to convert a logical unit from a first encryption state to a second encryption state is described, where the logical unit is partitioned into areas comprising a converted area, an unconverted area and a transition area.
Abstract: In one aspect, a method to convert a logical unit from a first encryption state to a second encryption state includes receiving a request to convert a logical unit from a first encryption state to a second encryption state, partitioning the logical unit into areas comprising a converted area, an unconverted area and a transition area, writing unconverted data in the transition area to a journal, converting the unconverted data from the first encryption state to the second encryption state and writing the converted data to the logical unit.

92 citations


Journal ArticleDOI
TL;DR: The logic as CSL is introduced which provides a powerful means to characterize execution paths of Markov chains with actions and state labels and it is shown that even the state-based fragment of asCSL is strictly more expressive than CSL if time intervals starting at zero are employed.
Abstract: In the past, logics of several kinds have been proposed for reasoning about discrete-time or continuous-time Markov chains. Most of these logics rely on either state labels (atomic propositions) or on transition labels (actions). However, in several applications it is useful to reason about both state properties and action sequences. For this purpose, we introduce the logic as CSL which provides a powerful means to characterize execution paths of Markov chains with actions and state labels. asCSL can be regarded as an extension of the purely state-based logic CSL (continuous stochastic logic). In asCSL, path properties are characterized by regular expressions over actions and state formulas. Thus, the truth value of path formulas depends not only on the available actions in a given time interval, but also on the validity of certain state formulas in intermediate states. We compare the expressive power of CSL and asCSL and show that even the state-based fragment of asCSL is strictly more expressive than CSL if time intervals starting at zero are employed. Using an automaton-based technique, an asCSL formula and a Markov chain with actions and state labels are combined into a product Markov chain. For time intervals starting at zero, we establish a reduction of the model checking problem for asCSL to CSL model checking on this product Markov chain. The usefulness of our approach is illustrated with an elaborate model of a scalable cellular communication system, for which several properties are formalized by means of asCSL formulas and checked using the new procedure

84 citations


Proceedings ArticleDOI
04 Jun 2007
TL;DR: It is argued that implicitly parallel programming models are critical for addressing the software development crises and software scalability challenges for many-core microprocessors.
Abstract: This paper argues for an implicitly parallel programming model for many-core microprocessors, and provides initial technical approaches towards this goal. In an implicitly parallel programming model, programmers maximize algorithm- level parallelism, express their parallel algorithms by asserting high-level properties on top of a traditional sequential programming language, and rely on parallelizing compilers and hardware support to perform parallel execution under the hood. In such a model, compilers and related tools require much more advanced program analysis capabilities and programmer assertions than what are currently available so that a comprehensive understanding of the input program's concurrency can be derived. Such an understanding is then used to drive automatic or interactive parallel code generation tools for a diverse set of parallel hardware organizations. The chip-level architecture and hardware should maintain parallel execution state in such a way that a strictly sequential execution state can always be derived for the purpose of verifying and debugging the program. We argue that implicitly parallel programming models are critical for addressing the software development crises and software scalability challenges for many-core microprocessors.

Proceedings ArticleDOI
26 Mar 2007
TL;DR: A novel register design which can detect and correct soft errors, which can be operated as a simple scan flip-flop or scan hold flip- flop and thus is useful for system testability purposes.
Abstract: Radiation from outer space comprising of charged particles can affect transistors in integrated circuits resulting in a change in the state of transistors. This creates a temporary transient effect that corrupts logic within a circuit, and hence it is called a single event upset (SEU). The SEU if captured may lead to soft error. With the progress of microelectronic technology, the shrinkage of transistor sizes is enabling the integration of more transistors in a circuit, making them more vulnerable to soft errors. Any future attempt toward scaling will have to address the problems of circuit reliability which is affected by the increasing number of failures arising from soft errors. In this paper the authors present a novel register design which can detect and correct soft errors. The authors add a redundant latch to the existing structure of a flip-flop and functional data is simultaneously registered at multiple latches. The content of these multiple latches are fed to a majority voter, and if the content of any of these latches is corrupted by a soft error, it is filtered out through the majority voting circuit. This design provides tolerance over the entire vulnerability region of a flip-flop unlike other published solutions. This design can be operated as a simple scan flip-flop or scan hold flip-flop and thus is useful for system testability purposes. The detection and correction operation takes place concurrently, with 23% degradation in system performance

Patent
28 Sep 2007
TL;DR: In this article, a service processor identifies a program to be patched and an associated patch for the program, and the patch is loaded into memory, including applying relocation fix-ups to the patch.
Abstract: Methods and apparatuses enable in-memory patching of a program loaded in volatile memory. A service processor identifies a program to be patched and an associated patch for the program. The patch is loaded into memory, including applying relocation fix-ups to the patch. The service processor directs the program to the patch in place of the segment of the program to be patched. The program implements the patch while maintaining program state, and without suspending execution of the program.

Journal ArticleDOI
TL;DR: In this paper, the buck-boost Z-source power conversion concept is integrated into the current source (CS) inverter topology to develop single and three-phase z-source CS inverters.
Abstract: Traditionally, current source (CS) inverters have been adopted for use in medium and high power industry applications. These inverters, however, support only current-buck dc-ac power conversion and need a relatively complex modulator, as compared to conventional voltage source (VS) inverters. To address these limitations, this paper presents an integration of the buck-boost Z-source power conversion concept to the CS inverter topology to develop single- and three-phase Z-source CS inverters. For their efficient control, the paper starts by evaluating different carrier-based reference formulations to identify different inverter state placement possibilities. The paper then proceeds to design appropriate "reference-to-switch" assignments or logic equations for mapping out the correct CS gating signals, allowing a simple carrier-based modulator to control a Z-source CS inverter with complications such as commutation difficulties and "many-to-many" state assignments readily resolved. The developed system can be implemented using a digital signal processor with an embedded VS pulse-width modulator and an external programmable logic device, hence offering a competitive solution for medium power single and three-phase buck-boost power conversion. Theory, simulation, and experimental results are presented in the paper

Patent
Daniel Hiltgen1, Rene W. Schmidt1
19 Dec 2007
TL;DR: In this article, the authors present a method including: (a) representing virtual primary disk data and state data of a virtual machine in a unit of storage; (b) exposing the virtual primary data of the virtual machine to a guest of the VM to allow the guest to access the VM's data; and (c) preventing the guest from accessing the state data for the VM.
Abstract: One embodiment of the present invention is a method including: (a) representing virtual primary disk data and state data of a virtual machine in a unit of storage; (b) exposing the virtual primary disk data of the virtual machine to a guest of the virtual machine to allow the guest to access the virtual primary disk data; and (c) preventing the guest from accessing the state data for the virtual machine.

Patent
Shih-Chung Lee1
03 Jul 2007
TL;DR: Coarse/fine programming of non-volatile memory is provided in this article, where memory cells are programmed at a first rate of programming prior to reaching a coarse verify level for their intended state and a second rate of programming after reaching the coarse verified level but before reaching the final verified level for the intended state.
Abstract: Coarse/fine programming of non-volatile memory is provided in which memory cells are programmed at a first rate of programming prior to reaching a coarse verify level for their intended state and a second rate of programming after reaching the coarse verify level but before reaching the final verify level for their intended state. Large sub-threshold swing factors associated with smaller memory cells can affect the accuracy of sense operations, particularly when sensing at a fine verify level after sensing at a coarse verify level without pre-charging the bit line between the different sensings. Different reference potentials are utilized when sensing at a coarse verify level and a final verify level. The different between the reference potentials can compensate for any discharge of the bit line during the coarse level sensing.

Patent
03 Jul 2007
TL;DR: In this paper, a computer system periodically determines utilization information for the computer system and adjusts the performance state according to the utilization information, and if a performance increase is required, the system always goes to the maximum performance state.
Abstract: A computer system has multiple performance states. The computer system periodically determines utilization information for the computer system and adjusts the performance state according to the utilization information. If a performance increase is required, the computer system always goes to the maximum performance state. If a performance decrease is required, the computer system steps the performance state down to a next lower performance state.

Proceedings ArticleDOI
10 Sep 2007
TL;DR: The ability to symbolically execute a commonly used library class, specifically a string, at an abstract level is demonstrated by abstracting away the implementation details of strings using finite-state automata, which can scale to more complex programs.
Abstract: Forward symbolic execution is a technique for program analysis that explores the execution paths of a program by maintaining a symbolic representation of the program state. Traditionally, applications of this technique have focused on symbolically representing only primitive data types, while more recent extensions have expanded to reference types. We demonstrate the ability to symbolically execute a commonly used library class, specifically a string, at an abstract level. By abstracting away the implementation details of strings using finite-state automata, symbolic execution can scale to more complex programs. This technique can be applied to programs which generate complicated strings, such as SQL database queries.

Proceedings ArticleDOI
26 Sep 2007
TL;DR: This paper investigates the use of genetic algorithms in test data generation for the chosen paths in the state machine, so that the input parameters provided to the methods trigger the specified transitions.
Abstract: Although a lot of research has been done in the field of state-based testing, the automatic generation of test cases from a functional specification in the form of a state machine is not straightforward. This paper investigates the use of genetic algorithms in test data generation for the chosen paths in the state machine, so that the input parameters provided to the methods trigger the specified transitions.

Patent
12 Apr 2007
TL;DR: In this paper, a method and system for simulating state retention of a register-transfer-level (RTL) design is presented. But the method is limited to the case where the power domains are controlled by a set of power control signals through a power manager logic.
Abstract: Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, identifying one or more power domains of the circuit using the netlist description and the power information specifications, associating the one or more power domains and the power information specifications in the RTL design environment, where the one or more power domains are controlled by a set of power control signals through a power manager logic, and simulating state retention behavior in response to variations in power applied to the power domain.

Patent
10 Sep 2007
TL;DR: In this paper, a text editor containing lines of text of a script is received, commands to control objects in a simulation are identified in the text in the editor, a state of the simulation is updated in accordance with the input and the commands, and the simulation can be displayed in a graphical display.
Abstract: Input from a text editor containing lines of text of a script is received, commands to control objects in a simulation are identified in the lines of text in the editor, a state of the simulation is updated in accordance with the input and the commands, and the simulation is displayed in a graphical display. A computer program enables a user to walk around in a simulation, with the events in the simulation determined by pre-written scripts.


Patent
Robert Alan Flavin1
31 May 2007
TL;DR: In this article, a shared state manager (SSM) for collaboration includes an updating module for updating shared state of data based on a request to edit the data made by a client, and a notifying module for, upon updating the shared state, notifying another client of the updated state.
Abstract: A shared state manager (SSM) for collaboration includes an updating module for updating a shared state of data based on a request to edit the data made by a client, and a notifying module for, upon the updating the shared state, notifying another client of the updated state.

Patent
21 Mar 2007
TL;DR: In this paper, the authors propose a fault reporting method for mesh access point failure reporting, which includes receiving a fault indication indicating one or more failures, collecting fault data related to the one or multiple failures or a state of the access point, and passing the fault data to the RFID tag, which wirelessly transmits messages relating to the fault.
Abstract: Mesh access point fault reporting. In particular implementations, a method includes receiving a fault indication indicating one or more failures; collecting fault data related to the one or more failures or a state of the mesh access point; and passing the fault data to the RFID tag, which wirelessly transmits messages relating to the fault.

Patent
10 Jan 2007
TL;DR: In this paper, the state data associated with the simulation model and the control system logic are synchronized with a timing and control mechanism and a simulation of the controller is executed, and a graphical user interface is provided to adjust the simulation settings and establish new connections with input/output components to be utilized in simulation.
Abstract: Systems and methods for simulating dynamic feedback control systems that include establishing a connection via a common access to a shared memory between the control system logic of a controller to be emulated and a simulation model. State data from a previous simulation associated with the control system logic and the simulation model is retrieved from memory to initialize another simulation run. The state data associated with the simulation model and the control system logic are then synchronized with a timing and control mechanism and a simulation of the controller is executed. A graphical user interface may also be provided to allow a user to adjust the simulation settings and establish new connections with input/output components to be utilized in simulation.

Patent
28 Feb 2007
TL;DR: In this paper, a method for storing multiple types of information, including information representative of a content of a persistent memory entity at a certain point in time, and information representing a state of a virtual machine at the same time, is proposed.
Abstract: A method for storing multiple types of information, the method includes: storing information representative of a content of a persistent memory entity at a certain point in time; and storing information representative of a state of a virtual machine at the certain point in time. A computer program product including a computer usable medium including a computer readable program, wherein the computer readable program when executed on a computer causes the computer to: store information representative of a content of a persistent memory entity at a certain point in time; and store information representative of a state of a virtual machine at the certain point in time.


Journal ArticleDOI
TL;DR: The proposed heuristic is based on a branch-and-bound search technique and identification of sets of compatible states of a given ISFSM specification and has obtained results as good as the best exact method in the literature but with significantly better run-times.

Patent
26 Jun 2007
TL;DR: In this article, a state controller allows each application to operate in a stateful mode, a stateless mode, or a combined mode, and the mode for an application can be specified during configuration/installation of the business system, removing the need to specify communication modes for applications during design and development of the applications and business system.
Abstract: Methods and systems for specifying the state of an application interface during configuration of the business system are provided. A state controller can manage communication between application interfaces and interface proxies. Each interface proxy replicates the services exposed by an application interface associated with backend applications in a business system. The state controller allows each application to operate in a stateful mode, a stateless mode, or a combined mode. The mode for an application can be specified during configuration/installation of the business system, removing the need to specify communication modes for applications during design and development of the applications and business system. The use of an interface proxy allows user interface (frontend) application to be developed and/or configured individually, and without regard to the communication mode used by the backend applications.

Patent
27 Nov 2007
TL;DR: In this paper, a presence server comprises a state machine to maintain current machine states for a plurality of users, and a mapper to map the current machine state for each user to a corresponding presence status.
Abstract: A presence server comprises a state machine to maintain current machine states for a plurality of users, and a mapper to map the current machine state for each user to a corresponding presence status.