Showing papers on "State (computer science) published in 2012"

Boolean Function Complexity: Advances and Frontiers

Abstract: Boolean circuit complexity is the combinatorics of computer science and involves many intriguing problems that are easy to state and explain, even for the layman. This book is a comprehensive description of basic lower bound arguments, covering many of the gems of this complexity Waterloo that have been discovered over the past several decades, right up to results from the last year or two. Many open problems, marked as Research Problems, are mentioned along the way. The problems are mainly of combinatorial flavor but their solutions could have great consequences in circuit complexity and computer science. The book will be of interest to graduate students and researchers in the fields of computer science and discrete mathematics.

Transferring application state across devices

Abstract: A first client device or system performs a method that includes retaining in memory registration information for a respective application indicating the respective application is registered for sharing application state with other client devices or systems. The method further includes storing an application state of a respective application, and detecting a transfer triggering condition. The transfer triggering condition includes presence of a second client device or system within a predefined proximity of the first client device or system, and the predefined proximity is a predefined proximity for near field communication. Furthermore, upon detecting the triggering condition, the first client device or system determines, in accordance with the stored registration information, that the respective application is registered for application state sharing, and transmits the application state of the respective application to the second client device or system.

Declarative Networking

Abstract: Declarative Networking is a programming methodology that enables developers to concisely specify network protocols and services, which are directly compiled to a dataflow framework that executes the specifications. This paper provides an introduction to basic issues in declarative networking, including language design, optimization, and dataflow execution. We present the intuition behind declarative programming of networks, including roots in Datalog, extensions for networked environments, and the semantics of long-running queries over network state. We focus on a sublanguage we call Network Datalog (NDlog), including execution strategies that provide crisp eventual consistency semantics with significant flexibility in execution. We also describe a more general language called Overlog, which makes some compromises between expressive richness and semantic guarantees. We provide an overview of declarative network protocols, with a focus on routing protocols and overlay networks. Finally, we highlight related work in declarative networking, and new declarative approaches to related problems.

Secure two-party computation in sublinear (amortized) time

Abstract: Traditional approaches to generic secure computation begin by representing the function f being computed as a circuit. If f depends on each of its input bits, this implies a protocol with complexity at least linear in the input size. In fact, linear running time is inherent for non-trivial functions since each party must "touch" every bit of their input lest information about the other party's input be leaked. This seems to rule out many applications of secure computation (e.g., database search) in scenarios where inputs are huge.Adapting and extending an idea of Ostrovsky and Shoup, we present an approach to secure two-party computation that yields protocols running in sublinear time, in an amortized sense, for functions that can be computed in sublinear time on a random-access machine (RAM). Moreover, each party is required to maintain state that is only (essentially) linear in its own input size. Our approach combines generic secure two-party computation with oblivious RAM (ORAM) protocols. We present an optimized version of our approach using Yao's garbled-circuit protocol and a recent ORAM construction of Shi et al.We describe an implementation of our resulting protocol, and evaluate its performance for obliviously searching a database with over 1 million entries. Our implementation outperforms off-the-shelf secure-computation protocols for databases containing more than 218 entries.

Dynamic cryptography change system

Abstract: PROBLEM TO BE SOLVED: To achieve encryption processing that is high in integrity and secrecy of communication data in the constraint on a processing time.SOLUTION: A control device comprises: a requirement list storage unit which stores a security requirement for communication data corresponding to an application operating in the control device and a command used by the application; an evaluation result storage unit which stores an evaluation result associated with execution of a variety of encryption algorithms; an own device environment information storage unit which stores environment information indicating the state of the control device; and a cryptography selection unit which selects, from the variety of encryption algorithms, an encryption algorithm which encrypts the communication data and satisfies the security requirement, the evaluation result, and first environment information corresponding to an application having generated first communication data and a command used for generation of communication data by the application.

Method and apparatus for protecting a password of a computer having a non-volatile memory

Abstract: A method for protecting a password of a computer having a non-volatile memory is disclosed. A password is stored in a non-volatile memory of a computer. The computer is then transitioned to a power saving state. In response to a detection of an unauthorized access to the non-volatile memory during the power saving state transition, a password input is requested from a user. The computer returns to a power-on state from the power saving state when there is a success in authentication of the input password.

Temporal Logic Control of Discrete-Time Piecewise Affine Systems

Abstract: We present a computational framework for automatic synthesis of a feedback control strategy for a discrete-time piecewise affine (PWA) system from a specification given as a linear temporal logic (LTL) formula over an arbitrary set of linear predicates in the system's state variables. Our approach consists of two main steps. First, by defining appropriate partitions for its state and input spaces, we construct a finite abstraction of the PWA system in the form of a control transition system. Second, by leveraging ideas and techniques from LTL model checking and Rabin games, we develop an algorithm to generate a control strategy for the finite abstraction. While provably correct and robust to state measurements and small perturbations in the applied inputs, the overall procedure is conservative and expensive. The proposed algorithms have been implemented as a software package and made available for download. Illustrative examples are included.

Controlled remote state preparation of arbitrary two and three qubit states via the Brown state

Abstract: In this paper, several new protocols for the controlled remote state preparation (CRSP) by using the Brown state as the quantum channel are proposed. Firstly, we propose a CRSP protocol of an arbitrary two qubit state. Then, the CRSP protocol of an arbitrary three qubit state, which has rarely been considered by the previous papers, is investigated. The coefficients of the prepared states can be not only real, but also complex. To design these protocols, some useful and general measurement bases are constructed, which can greatly reduce the restrictions for the coefficients of the prepared states. The security analysis is provided in detail. Moreover, receiver's all recovery operations are summarized into a concise formula.

Restricting mobile device usage

Abstract: Systems and methods are provided for selectively restricting a mobile device. In one implementation, a visual capture can be to identify one or more indicators within the visual capture. Based on the indicators, an implementation of a restriction at the mobile device can be adjusted. In another implementation inputs can be processed to compute a determination, determination reflecting at least one of the in-vehicle role of the user as a driver and the in-vehicle role of the user as a passenger; and, an operation state of the mobile device can be modified based on such a determination. According to another implementation, one or more outputs can be projected from a mobile device, inputs can be received, and such inputs and outputs can be processed to determine a correlation between them. A restriction can then be modified based on the correlation.

Systems and methods for accessing an interaction state between multiple devices

Abstract: The present application discloses systems and methods for accessing digital content between multiple devices. The systems and methods may be directed to providing access to an interaction with a first application on a head-mounted display (HMD) to a second device. Contextual information relating information of the HMD and information associated with the interaction to describe an interaction state may be stored. A second device may be selected upon which the interaction state may be accessed and a determination of attributes of the second device may be made. The HMD may transfer to the second device the stored contextual information such that the second device may provide via the second application access to the interaction state. Information associated with a user input to the first application may also be transferred. In one example, the contextual information may describe an identified occurrence of digital content accessed via the first application.

Reducing power consumption by migration of data within a tiered storage system

Abstract: Mechanisms identify one or more first storage devices in a first tier of the tiered storage system that may be placed in a minimal power consumption state and identify one or more data segments stored on the one or more first storage devices that are most likely to be accessed during a period of time in which the one or more first storage devices are in the minimal power consumption state. The mechanisms migrate the one or more data segments to one or more second storage devices in one of the first tier or a second tier of the storage system and place the one or more first storage devices in the minimal power consumption state. Access requests to the one or more data segments are serviced by the one or more second storage devices while the one or more first storage devices are in the minimal power consumption state.

Symbolic bounded synthesis

Abstract: Synthesizing finite-state systems from full linear-time temporal logic (LTL) is an ambitious way to tackle the challenge of constructing correct-by-construction systems. One particularly promising approach in this context is bounded synthesis, originally proposed by Schewe and Finkbeiner, which in turn builds upon Safraless synthesis, as described by Kupferman and Vardi. Previous implementations of these approaches performed the computation either in an explicit way or used symbolic data structures other than binary decision diagrams (BDDs). In this paper, we reconsider BDDs as state space representation and use it as data structure for bounded synthesis. The key to this construction is the application of two novel optimisation techniques that decrease the number of state bits in such a representation significantly. The first technique uses signalling bits to connect sub-games representing the safety- and non-safety parts of the specification. The second technique is based on a closer analysis of the step of building a safety game from a universal automaton and uses a sufficient condition to remove some so-called counters from the state space of the game. We evaluate our approach on several benchmark suites and show that the new approach leads to a computation time improvement of several orders of magnitude.

Method and apparatus for synchronizing tasks performed by multiple devices

Abstract: Provided herein is a method, which may include an indication that is received that a view of a task is presented by a first device. State information may be provided to a second device to permit the second device to be synchronized with the first device and to present a view of the task, either the same view or a different view than that presented by the first device. Information may also be received relating to a change in state of the task that is provided by one of the devices while a first view of the task is presented thereupon. Further, updated state information may be provided to another one of the devices to cause the other device to remain synchronized and to update a second view of the task that is presented.

Binary translator with precise exception synchronization mechanism

Abstract: A source computer system with one instruction set architecture (ISA) is configured to run on a target hardware system that has its own ISA, which may be the same as the source ISA. In cases where the source instructions cannot be executed directly on the target system, the invention provides binary translation system. During execution from binary translation, however, both synchronous and asynchronous exceptions may arise. Synchronous exceptions may be either transparent (requiring processing action wholly within the target computer system) or non-transparent (requiring processing that alters a visible state of the source system). Asynchronous exceptions may also be either transparent or non-transparent, in which case an action that alters a visible state of the computer system needs to be applied. The invention includes subsystems, and related methods of operation, for detecting the occurrence of all of these types of exceptions, to handle them, and to do so with precise reentry into the interrupted instruction stream; by “precise” is meant that the atomic execution of the source instructions is guaranteed, and that the application of actions, including those that originate from asynchronous exceptions, occurs at the latest at the completion of the current source instruction at the time of the request for the action. The binary translation and exception-handling subsystems are preferably included as components of a virtual machine monitor which is installed between the target hardware system and the source system, which is preferably a virtual machine.

Method and apparatus for restoring an instance of a storage server

Abstract: Implementations of the present disclosure involve a system and/or method for gracelessly rebooting a storage appliance. The method and system includes a storage appliance in association with an event that will result in the loss of a state table from volatile memory that halts changes to at least one state table of the storage appliance. The state tables describe a plurality of file system states of one or more clients connected to the first storage appliance. The state information is written to a persistent memory of the storage appliance. The state table may then be repopulated using the state table information stored in persistent memory.

Method and apparatus for debugging programs

Abstract: A computer-implemented method, apparatus and computer program product for debugging programs, the method comprising: displaying a graphic waveform showing values of one or more state variables of a computer program being debugged in two or more points in time; receiving a user selection from points in time, of an indication to a selected point in time in execution from the graphic waveform; and resuming within a debugger an execution state of the computer program associated with the selected point in time.

Implications of CPU Caching on Byte-addressable Non-Volatile Memory Programming

Abstract: Byte-addressable non-volatile memory may usher in a new era of computing where in-memory data structures are persistent and can be reused directly across machine restarts. However, sudden failures complicate matters because a program state may partially reside in volatile buffers and caches as opposed to primary non-volatile memory. We study the implications of different CPU caching modes and show that a particular choice affects both programmability and performance of a program.

Safety Control of Hidden Mode Hybrid Systems

Abstract: In this paper, we consider the safety control problem for hidden mode hybrid systems (HMHSs), which are a special class of hybrid automata in which the mode is not available for control. For these systems, safety control is a problem with imperfect state information. We tackle this problem by introducing the notion of nondeterministic discrete information state and by translating the problem to one with perfect state information. The perfect state information control problem is obtained by constructing a new hybrid automaton, whose discrete state is an estimate of the HMHS mode and is, as such, available for control. This problem is solved by computing the capture set and the least restrictive control map for the new hybrid automaton. Sufficient conditions for the termination of the algorithm that computes the capture set are provided. Finally, we show that the solved perfect state information control problem is equivalent to the original problem with imperfect state information under suitable assumptions. We illustrate the application of the proposed technique to a collision avoidance problem between an autonomous vehicle and a human driven vehicle at a traffic intersection.

Microprocessor based power management system architecture

Abstract: An electronic system is disposed on a single integrated circuit including a plurality of power domains and a power control manager. Each power domain may be independently powered. The power control manager includes a set of control registers storing individual control bits, a power switch for each power domain and a programmable microprocessor. The programmable microprocessor controls the digital state of individual bits within the control registers thereby controlling the ON and OFF state of the corresponding power domain.

System and method for in-vehicle operator training

Abstract: An on-vehicle system for assessing an operator's efficiency of a vehicle, include sensors, an audiovisual display device, a processor and a data storage. The sensors measure or detect conditions of components of the vehicle, and convert the detected conditions into analog or digital information. The data storage stores program instructions, the analog or digital information from the sensors, and other data. The program instructions, when executed by the processor, control the on-vehicle system to determine a state of the vehicle within a vehicle's environment based on the analog or digital information from the sensors, determine whether one or more of a predetermined set of behaviors has occurred based on the determined state of a vehicle, assess performance of the determined one or more of the predetermined set of behaviors, and present the operator, via the audiovisual display device, a feedback based on the assessment.

On-Chip Clocking of Nanomagnet Logic Lines and Gates

Abstract: The nanomagnet logic (NML) devices considered here are variants of proposed components for the edge-driven, quantum-dot cellular automata device architecture, where the position of electrons on quantum dots was suggested as a mechanism for representing binary state. To control NML circuit components (e.g., gates and lines), to date, externally generated magnetic fields have served as a clock. The clock is used to make the magnets in a circuit ensemble transition to a metastable state, so fringing fields from individual devices can set the state of a neighboring device in accordance with a new input. However, such a clocking scheme is obviously not extensible to chip-level systems. For NML to be a viable candidate for digital systems, a mechanism for simultaneously modulating the energy barriers of a group of devices must be implemented “on-chip,” and guarantee unidirectional dataflow from circuit input to circuit output. We have experimentally demonstrated a CMOS-compatible clock, and used it to reevaluate all of the NML constructs required for a functionally complete logic set. All possible input combinations to said constructs were successfully considered. Experiments were designed to promote unidirectional dataflow.

Dynamic application migration

Abstract: A library operating system is employed in conjunction with an application in a virtual environment to facilitate dynamic application migration. An application executing in a virtual environment with a library operating system on a first machine can be suspended, and application state can be captured. Subsequently, the state can be restored and execution resumed on the first machine or a second machine.

Semi-autonomous liquid handling via on-chip pneumatic digital logic

Abstract: This report presents a liquid-handling chip capable of executing metering, mixing, incubation, and wash procedures largely under the control of on-board pneumatic circuitry. The only required inputs are four static selection lines to choose between the four machine states, and one additional line for power. State selection is simple: constant application of vacuum to an input causes the device to execute one of its four liquid handling operations. Programmed control of 31 valves, including fast coordinated cycling for peristaltic pumping, is accomplished by pneumatic digital logic circuits built out of microfluidic valves and channels rather than electronics, eliminating the need for the off-chip control machinery that is typically required for integrated microfluidics.

A small model theorem for rectangular hybrid automata networks

Abstract: Rectangular hybrid automata (RHA) are finite state machines with additional skewed clocks that are useful for modeling realtime systems. This paper is concerned with the uniform verification of safety properties of networks with arbitrarily many interacting RHAs. Each automaton is equipped with a finite collection of pointers to other automata that enables it to read their state. This paper presents a small model result for such networks that reduces the verification problem for a system with arbitrarily many processes to a system with finitely many processes. The result is applied to verify and discover counterexamples of inductive invariant properties for distributed protocols like Fischer's mutual exclusion algorithm and the Small Aircraft Transportation System (SATS).We have implemented a prototype tool called Passel relying on the satisfiability modulo theories (SMT) solver Z3 to check inductive invariants automatically.

Computer system, storage management computer, and storage management method

Abstract: A memory stores first configuration information indicating a plurality of logical storage areas and a first condition defining a state of a storage apparatus as a trigger for the storage apparatus to move data. A CPU acquires: a second condition defining a state of a computer as a trigger for the computer to move a first object, which is stored in a first logical storage area among the plurality of logical storage areas and performed by the computer, to another one of the plurality of logical storage areas; second configuration information associating the first object and the first logical storage area; first state information indicating a state of the plurality of logical storage areas; and second state information indicating a state of the first object. If a state of performing data movement is set, the CPU identifies a cause of the state of performing the data movement.

The Relationship Between Separation Logic and Implicit Dynamic Frames

Abstract: Separation logic is a concise method for specifying programs that manipulate dynamically allocated storage. Partially inspired by separation logic, Implicit Dynamic Frames has recently been proposed, aiming at first-order tool support. In this paper, we precisely connect the semantics of these two logics. We define a logic whose syntax subsumes both that of a standard separation logic, and that of implicit dynamic frames as sub-syntaxes. We define a total heap semantics for our logic, and, for the separation logic subsyntax, prove it equivalent the standard partial heaps model. In order to define a semantics which works uniformly for both subsyntaxes, we define the novel concept of a minimal state extension, which provides a different (but equivalent) definition of the semantics of separation logic implication and magic wand connectives, while also giving a suitable semantics for these connectives in implicit dynamic frames. We show that our resulting semantics agrees with the existing definition of weakest pre-condition semantics for the implicit dynamic frames fragment. Finally, we show that we can encode the separation logic fragment of our logic into the implicit dynamic frames fragment, preserving semantics. For the connectives typically supported by tools, this shows that separation logic can be faithfully encoded in a first-order automatic verification tool (Chalice).

Method for managing virtual machine, information processing apparatus, and medium for virtual machine management program

Abstract: A method of managing a virtual machine by an information processing system including one or more information processing apparatuses, the method includes: comparing one or more files used for operation of the virtual machine with one or more template files; and generating configuration information indicating a setting state of the virtual machine based on a result of the comparing.

Method and apparatus for increasing the functionality of an electronic device in a locked state

Abstract: An approach is provided for increasing the functionality of an electronic device when the device is in a locked state. The approach involves determining one or more applications for presentation at a device. The approach also involves determining that the device is in a locked state. The approach further involves processing and/or facilitating a processing of the one or more applications to cause, at least in part, presentation of the one or more applications in a user interface of the device associated with the locked state.