State (computer science)

About: State (computer science) is a research topic. Over the lifetime, 24436 publications have been published within this topic receiving 225733 citations.

Clairvoyant: a synthesis system for production-based specification

Abstract: This paper describes a new high-level synthesis system based on the hierarchical production based specification (PBS). Advantages of this form of specification are that the designer does not describe the control flow in terms of explicit states or control variables, and that the designer does not describe a particular form of implementation. The production-based specification also separates the specification of the control aspects and data-flow aspects of the design. The control is implicitly described via the production hierarchy, while the data-flow is described as action computations. This approach is a hardware analog of popular software engineering techniques. The Clairvoyant system automatically constructs a controlling machine from the PBS and this process is not impacted by the possibly exponentially larger deterministic state space of the designs. The encodings generated by the constructions compare favorably to encodings derived using graph-based state encoding techniques in terms of logic complexity and logic depth. These construction techniques utilize recent advances in BDD techniques. >

Portable electronic equipment

Abstract: PURPOSE:To eliminate an excessive write operation, and to prolong a physical service life as a memory, by detecting the data length of the storage data at the time of inputting a storage data string, and deciding whether or not all of data constituting the storage data string can be stored in an area to be stored CONSTITUTION:At the time of writing the storage data in the area, when a control element 15 decides that all of inputted storage data are impossible to be stored in the area, according to data string byte number information in an instruction data, the control element 5 outputs a response data which means a byte number information error, then a state is returned to an instruction data waiting state When it is decided that the are possible to be stored, the control element 15 checks the data string byte number information, and the number of bytes constituting the data string included the instruction data in such case, and when the value of the former is larger than that of the latter, the control element 15 outputs the response data which means the byte number information error, then the state is returned to the instruction data waiting state In a case of other than the above case, the value of the latter is subtracted from that of the former and a result is held as a residual quantity

Pomerantz, J., Nicholson, S., Belanger, Y., & Lankes, R. D. (in press). The current state of digital reference: Validation of a general digital reference model through a survey of digital reference services. Information Processing & Management. The Current State of Digital Reference: Validation of a General Digital Reference Model through a Survey of Digital Reference Services

Abstract: This paper describes a study conducted to determine the paths digital reference services take through a general process model of asynchronous digital reference. A survey based on the general process model was conducted; each decision point in this model provided the basis for at least one question. Common, uncommon, and wished-for practices are identified, as well as correlations between characteristics of services and the practices employed by those services. Identification of such trends has implications for the development of software tools for digital reference. This study presents a snapshot of the state-of-the-art in digital reference as of late 2001-early 2002, and validates the general process model of asynchronous digital reference.

Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system

Abstract: The present invention relates generally to a protocol engine for use in a multiprocessor computer system. The protocol engine, which implements a cache coherence protocol, includes a clock signal generator for generating signals denoting interleaved even clock periods and odd clock periods, a memory transaction state array for storing entries, each denoting the state of a respective memory transaction, and processing logic. The memory transactions are divided into even and odd transactions whose states are stored in distinct sets of entries in the memory transaction state array. The processing logic has interleaving circuitry for processing during even clock periods the even memory transactions and for processing during odd clock periods the odd memory transactions.

Speculative execution of test patterns in a random test generator

Abstract: Presented is a computer-based test system and method for generating and improving the effectiveness of test cases for a model or an implementation of a computer architecture. The system includes an architectural model configured to model the requirements of the computer architecture and a behavior model configured to model the implementation of the computer architecture, wherein the behavioral model is designed to conform with the computer architecture. Further included is a simulator configured to simulate the operation of the behavioral model in response to a test pattern and to provide a behavioral model state. A random test generator is configured to test aspects of the architectural model and to generate and provide test patterns to the simulator according to the behavioral model state provided by the simulator. The random test generator provides the ability to store a pre-simulation behavioral model state and reset the simulator to the pre-simulation behavioral model state at a later time. The system may further include a history of previous events from which the rate at which an event occurs may be controlled.