State (computer science)

About: State (computer science) is a research topic. Over the lifetime, 24436 publications have been published within this topic receiving 225733 citations.

Input to locked computing device

Abstract: A method comprises: receiving, at a computing device 102 that is in a locked state, one or more user inputs 110 to unlock the device and to execute at least one command that is different from a command for unlocking the device; executing in response to the user inputs to unlock the device an unlocking operation 114 to convert the device from a locked state to an unlocked state; and executing the at least one command 112 in response to receiving the user inputs to execute the at least one command, so that its results 116 are first displayed on the device to a user automatically after the device changes from the locked state to the unlocked state. A system can thus perform in parallel an unlocking operation and a user-requested operation; for example, a user can simultaneously perform an action, instigated by a touch or voice input, and unlock the device. Multiple actions (354 in Figure 3B) may be available at the same time.

Symbolic model checking for real-time systems

Abstract: Finite-state programs over real-numbered time in a guarded-command language with real-valued clocks are described. Model checking answers the question of which states of a real-time program satisfy a branching-time specification. An algorithm that computes this set of states symbolically as a fixpoint of a functional on state predicates, without constructing the state space, is given. >

A hybrid nanomemristor/transistor logic circuit capable of self-programming.

Abstract: Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing.

Logic-Based Models for the Analysis of Cell Signaling Networks

Abstract: Computational models are increasingly used to analyze the operation of complex biochemical networks, including those involved in cell signaling networks. Here we review recent advances in applying logic-based modeling to mammalian cell biology. Logic-based models represent biomolecular networks in a simple and intuitive manner without describing the detailed biochemistry of each interaction. A brief description of several logic-based modeling methods is followed by six case studies that demonstrate biological questions recently addressed using logic-based models and point to potential advances in model formalisms and training procedures that promise to enhance the utility of logic-based methods for studying the relationship between environmental inputs and phenotypic or signaling state outputs of complex signaling networks.

Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system

Abstract: An emulation system and method that reduces or eliminates the number of timing errors such as hold time violations when implementing a netlist description of an integrated circuit The emulation system comprises a plurality of reprogrammable logic circuits and a plurality of reprogrammable interconnect circuits The netlist description is optimized to reduce the number of timing violations by removing the occurences of gated clocks from the netlist, partitioning the netlist description by taking into account the occurence of timing violations and ensuring that retain state nets are implemented properly