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State (computer science)

About: State (computer science) is a research topic. Over the lifetime, 24436 publications have been published within this topic receiving 225733 citations.


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Patent
08 Oct 1985
TL;DR: A language structure and translator specifically adapted for use in constructing computer programs for controlling chemical and physical processing is described in this paper, where Graphical symbols are employed to draw the eye to critical features in the control program and to lead the eye through critical interrelationships among the several commands of a complicated control system.
Abstract: A language structure and translator specifically adapted for use in constructing computer programs for controlling chemical and physical processing. The translator converts to compilable code programs written as statements expressing control intentions or results. Each textual function and statement is expressed as a data structure which expresses the function, as configured, and the state and values most recently calculated for the relevant variables. Provision is made for treating the program structure (i.e., control connections, program order and components, etc.) as a part of the dynamic state of the application. Graphical symbols, or icons, are employed to draw the eye to critical features in the control program and to lead the eye through critical interrelationships among the several commands of a complicated control system. At the same time, the translator treats the keystrokes generating these icons as statements (i.e., commands) which define the relationships among other associated program statements (which are usually textual commands), to control the order in which the operations represented by those statements are executed.

69 citations

Patent
25 Jan 2011
TL;DR: In this paper, a method for writing updated data into a flash memory module having a plurality of physical pages is provided, wherein each physical page is the smallest writing unit of the flash memory.
Abstract: A method for writing updated data into a flash memory module having a plurality of physical pages is provided, wherein each physical page is the smallest writing unit of the flash memory module. The method includes partitioning a physical page into storage segments and configuring a state mark for each storage segment, wherein the state marks indicate the validity of data stored in the storage segments. The method also includes writing the updated data into at least one of the storage segments and changing the state mark corresponding to the storage segment containing the updated data, wherein the state mark corresponding to the storage segment containing the updated data indicates a valid state, and the state marks corresponding to the other storage segments of the physical page not containing the updated data indicate an invalid state. Thereby, the time for writing data into a physical page is effectively shortened.

69 citations

Patent
30 Jun 1994
TL;DR: In this article, the authors propose a suspend/resume/standby (SRS) power management scheme for a computer system having four states of power management: a normal operating state, a standby state, and an off state.
Abstract: A computer system having four states of power management: a normal operating state, a standby state, a suspend state, and an off state. The standby state is characterized by devices, such as a video controller and a hard drive, being placed into a low-power mode transparent to the operating system and the applications executing on the computer system. The suspend state is characterized by executing code being interrupted and the state of the computer system being saved to a file on the hard drive in such a manner that system power may be removed after the state of the computer system is saved to the hard drive. Later, after system power is restored, the state of the computer system is resumed by reading from the hard drive and loading it in such a manner that the operating system and application programs are not adversely affected. The normal operating state and the off state correspond to the typical on and off states of more conventional computer systems. The suspend/resume/standby feature is implemented at a low cost using many standard components.

69 citations

Patent
26 Jan 1996
TL;DR: In this paper, a register transfer level (RTL) model is created using an object-oriented programming language, where a logic circuit can be represented by a hierarchy of objects ("modules") each having representation of state elements, input signals, output signals and internal signals.
Abstract: A register transfer level (RTL) model is created using an object-oriented programming language. In that RTL model, a logic circuit can be represented by a hierarchy of objects ("modules") each having representation of state elements, input signals, output signals and internal signals. Each object is also provided member functions for initializing, for loading a new state and for generating a next state. These modules are collected in a linked list. In the beginning of simulation, each object is initialized as the linked list is traversed. Then, a consistent next state for the RTL model is obtained by generating a state next based on the initial state. Simulation proceeds by alternately traversing the linked list to load a new state into each module, and traversing the linked list to generate the next state for each module. The step of traversing the linked list to generate the next state of each module may require multiple executions to ensure convergence.

69 citations

Patent
19 Nov 1997
TL;DR: In this article, the authors propose a data processing system on an integrated circuit equipped with a microprocessor and a peripheral device together with an emulation unit for enabling the debug and emulation of integrated circuit at the time of connection to an external test system.
Abstract: PROBLEM TO BE SOLVED: To provide a data processing system on an integrated circuit equipped with a microprocessor and a peripheral device together with an emulation unit for enabling the debug and emulation of integrated circuit at the time of connection to an external test system. SOLUTION: A microprocessor 1 has fetch/decode units 10a-10c and an instruction execution pipeline provided with plural execution stages related to the unit of function execution. Since the pipeline of microprocessor 1 is not protected, the waiting time of access to a data memory 22 and register files 20 (20a and 20b) can be utilized by a system program code stored in an instruction storage device 23. An emulation unit 50 performs operation through a method for avoiding any state such as the generation of unrelated operation to affect the memories 22-23 and peripheral devices 60-61 during emulation.

69 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20251
202426
202314,059
202232,515
2021467
2020690