State (computer science)

About: State (computer science) is a research topic. Over the lifetime, 24436 publications have been published within this topic receiving 225733 citations.

History-less checking of dynamic integrity constraints

Abstract: An efficient implementation method is described for dynamic integrity constraints formulated in past temporal logic. Although the constraints can refer to past states of the database, their checking does not require that the entire database history be stored. Instead, every database state is extended with auxiliary relations that contain the historical information necessary for checking constraints. Auxiliary relations can be implemented as materialized relational views. The author analyzes the computational cost of the method and outlines how it can be implemented by using existing database technology. Related work on dynamic integrity constraints is surveyed. >

Field programmable gate array with integrated debugging facilities

Abstract: A number of enhanced logic elements (LEs) are provided to form a FPGA. Each enhanced LE comprises a multiple input-single output truth table, and a complementary pair of master-slave latches having a data, a set and a reset input. Each enhanced LE further comprises a plurality of multiplexers and buffers, and control logic. Additionally, the improved FPGA further comprises a network of crossbars, a context bus, a scan register, and a plurality of trigger circuitry. As a result, each LE may be individually initialized, its signal state frozen momentarily, the frozen state be read, trace data be output, and trigger inputs be conditionally generated. Furthermore, the enhanced LEs may be used for "level sensitive" as well as "edge sensitive" circuit design emulations.

Optimized synthesis of self-testable finite state machines

Abstract: A synthesis procedure for self-testable finite state machines is presented. Testability comes under consideration when the behavioral description of the circuit is being transformed into a structural description. To this end, a novel state encoding algorithm, as well as a modified self-test architecture, is developed. Experimental results show that this approach leads to a significant reduction of hardware overhead. Self-testing circuits generally employ linear feedback shift registers for pattern generation. The impact of choosing a particular feedback polynomial on the state encoding is discussed. >

Fast sense amplifier

Abstract: An integrated circuit sense amplifier includes a pair of complementary inputs for receiving a pair of complementary data signals which are input to a CMOS flip-flop having its output nodes connected to a logic low through a first transistor and its high side connected to a logic high through a second transistor. The first transistor is on when data signals are not being sensed, holding the nodes in a no-current, logic low state. The first transistor turns off and the second transistor turns on just prior to the arrival of a signal, precharging the nodes to an intermediate voltage, permitting the flip-flop to latch more quickly to a full-logic output when the signal arrives. A preamp may be interposed between the complementary inputs and the latch. The preamp inputs and outputs are precharged to voltage levels near or between their anticipated final levels, so that they reach their final levels quickly when the data signal arrives. The flip-flop output nodes may be connected to a tristate output circuit, which is also precharged to an intermediate level, enabling it to reach its full output more quickly.

Semiconductor memory device

Abstract: PURPOSE:To prevent wrong destruction of data and security leak in a semiconductor memory independently of a microprocessor by providing a comparing means which compares the password of the memory with that of a latch to set or inhibit a prescribed mode in the semiconductor memory. CONSTITUTION:When the input password coincides with the set password, a read control signal is outputted from a comparing circuit 8 to an output line 15 and a semiconductor 4 is to the readable state. This read control signal is supplied to a control circuit 3 also and it is judged that data read is permitted. The control circuit 3 sends an address signal to the semiconductor memory 4 through an address bus 11 and reads desired data from the semiconductor memory 4 through a data bus 10. If the input password does not coincide with the set password, the comparing circuit 8 does not output the read control signal because a flag of 'read inhibition' is stored in a password memory 7. Thus, the security of stored data is kept and destruction of stored data or the like is prevented.