State (computer science)

About: State (computer science) is a research topic. Over the lifetime, 24436 publications have been published within this topic receiving 225733 citations.

System and Method for Checking the Integrity of Computer Program Code

Abstract: A system (100) includes a processor having a trace port, a memory coupled to the processor (104), and a software integrity checking ('SIC') logic coupled to the memory and the trace port. The trace port provides data regarding an execution state of a most recently executed instruction. The SIC logic is operable to check integrity of addresses of instructions in a code sequence stored in the memory and executable on the processor, and to check integrity of execution states of the executed instructions.

Control design for hybrid systems with TuLiP: The Temporal Logic Planning toolbox

Abstract: This tutorial describes TuLiP, the Temporal Logic Planning toolbox, a collection of tools for designing controllers for hybrid systems from specifications in temporal logic. The tools support a workflow that starts from a description of desired behavior, and of the system to be controlled. The system can have discrete state, or be a hybrid dynamical system with a mixed discrete and continuous state space. The desired behavior can be represented with temporal logic and discrete transition systems. The system description can include uncontrollable variables that take discrete or continuous values, and represent disturbances and other environmental factors that affect the dynamics, as well as communication signals that affect controller decisions.

Differential dynamic content addressable memory and high speed network address filtering

Abstract: The invention relates to a three-state content addressable memory cell with a comparison element operationally connected to the match line output that outputs a signal having (i) a first logic state in response to two inputs having different logic states and (ii) a second logic state in response to two inputs having the same logic states, a first data storage (element) having an input operationally connected to a first data input line and an output operationally connected to said comparison element, a second data storage element having an input operationally connected to a second data input line and an output operationally connected to an input to said comparison element, said content addressable memory cell storing a masked state by storing the same logic state on said first and said second storage elements, said match line output having no direct connection to said first and second data storage elements thereby providing operational isolation between said match line output and said storage elements.

Small and power-efficient cache that can provide data for background DMA devices while the processor is in a low-power state

Abstract: Small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data. The microprocessor implements one or more processors having associated cache systems (such as various arrangements of first-, second-, and higher-level caches).

Semiconductor memory with improved test mode

Abstract: An integrated circuit memory is disclosed which has a parallel test read mode. The memory includes comparators for comparing multiple data words, on a bit-by-bit basis, during the parallel read mode, with the result of the comparison used to enable or disable the output buffers. In test mode, in the event of a failed parallel test comparison, the comparator causes the output buffers to go into a high-impedance state; for a passing parallel test, the actual data state is presented by the output terminals The comparison circuitry is in parallel with the output data path, so that the output data path is not adversely affected by the test circuitry, and so that the access time in test mode is the same as the access time during normal operation (assuming a passing test). The technique may be adapted to wide parallel test schemes.