scispace - formally typeset
Search or ask a question
Topic

State (computer science)

About: State (computer science) is a research topic. Over the lifetime, 24436 publications have been published within this topic receiving 225733 citations.


Papers
More filters
Journal ArticleDOI
TL;DR: In this article, the authors examine gender-based violence against women, including gender-motivated murders (feminicides), the everyday acts that can result in their deaths, and impunity for these crimes.
Abstract: Increasing exclusion and inequality in Honduras have posed escalating security risks for women in their homes and on the streets. In this article, we examine gender-based violence against women, including gender-motivated murders (feminicides), the everyday acts that can result in their deaths, and impunity for these crimes. Rather than analyzing these murders as interpersonal acts or linking them to economic deprivation, we examine the actions and inactions of the state that have amplified violence in the lives of Honduran women. We distinguish between the state’s acts of omission and acts of commission in order to identify the political responsibility and failures that create a fertile ground for these killings. A context of multisided violence that facilitates extreme violence in the lives of women is present in Honduras, especially considering the diminishing power of civil society groups and increased political repression after the 2009 coup. We identify root causes of the wide (and widening) gap between laws on the books—which have been passed mostly to satisfy international and domestic organizations pushing for change—and laws in action, that is, implementation on the ground. Although we focus on Honduras, we note similar experiences of extreme violence in Guatemala, El Salvador, and in other countries in the Latin American region.

61 citations

Patent
04 Sep 2002
TL;DR: In this article, configurable interconnect resources of field programmable gate arrays (FPGA's) are tested by configuring at least some of the lookup tables (LUT's), registers and input signal acquirers to implement one or more sequential state machines that feed back their current states via the interconnect conductors to the inputs of the LUT's.
Abstract: Configurable interconnect resources of field programmable gate arrays (FPGA's) are tested by configuring at least some of the lookup tables (LUT's), registers and input signal acquirers to implement one or more sequential state machines that feed back their current states via at least some of the interconnect conductors to the inputs of the LUT's. The fedback signals are decoded by the LUT's for defining next-states of the one or more sequential state machines. Each sequential state machine may be programmed to sequentially step through a number of unique states, where the unique states challenge capabilities of the interconnect conductors to toggle through combinations of different signal levels. The sequential state machines are exercised to sequentially step through plural ones of their unique states. At least one of the stepped-into states is sensed and analyzed after a predefined number of steps have been taken in order to determine whether the detected state matches the expected state for the predefined number of steps. If it does not, that is taken to indicate that a defect exists in the under-test FPGA. Plural sequential state machines can be exercised in parallel within a given FPGA so that large numbers of interconnect resources can be simultaneously challenged.

61 citations

Patent
Mark R. Enstrom1
25 Feb 1993
TL;DR: In this article, a system and method for automatically identifying and configuring interface boards connected to a computer bus is described, where each interface board contains a pair of interface ports that can be addressed by the system and a unique identification address.
Abstract: A system and method for automatically identifying and configuring interface boards connected to a computer bus is disclosed. Each interface board contains a pair of interface ports that can be addressed by the system and a unique identification address. The interface boards are instructed to serially read the identification address and place a logic 10 in the two least significant bits of the data bus if the first data bit is a logic one. The serial read instruction is performed twice for each data bit in the identification address with a logic 01 data pattern placed on the data bus for the second serial read to assure that a floating data bus is not causing false readings. If no interface board responds to any particular read identification instruction, the system assigns a logic zero for that particular bit of the identification address. Any interface board not having a logic one for a particular first data bit in the identification automatically places itself in a disabled state if the first and second serial read instructions indicate that another interface board did have a logic one for that particular data bit of the identification address. By the time that the system has read all of the identification bits, one and only one interface board will have been identified and enabled. The system can read registers on the interface board to determine which resources are required for operation of that board and assigns parameters such as I/O address, interrupt line, and data channel line. The system enables the other previously disabled interface boards and repeats the identification instructions until all interface boards have been identified and configured.

61 citations

Journal ArticleDOI
Gerard J. Holzmann1
TL;DR: The algorithm derived in this manner works in a fixed-size memory arena (it will never run out of memory), it is up to 2 orders of magnitude faster than the previous methods, and it has superior coverage of the state space when analyzing large protocol systems.
Abstract: This paper studies the four basic types of algorithm that, over the last 10 years, have been developed for the automated verification of the logical consistency of data communication protocols. The algorithms are compared on memory usage, CPU time requirements, and the quality of the search for errors. It is shown that the best algorithm, according to above criteria, can be improved further in a significant way, by avoiding a known performance bottleneck. The algorithm derived in this manner works in a fixed-size memory arena (it will never run out of memory), it is up to 2 orders of magnitude faster than the previous methods, and it has superior coverage of the state space when analyzing large protocol systems. The algorithm is the first for which the search efficiency (the number of states analyzed per second) does not depend on the size of the state space: there is no time penalty for analyzing very large state spaces. The practicality of the new algorithm has been tested in the verification of portions of AT&T's 5ESS® switch. The models analyzed in these tests generated up to 250 million composite system states, that could be analyzed effectively in an hour's worth of CPU time on a large mainframe computer.

60 citations

Journal ArticleDOI
TL;DR: A state transition model for the optimization of query processing in a distributed database system that permits significant reductions of the necessary computations by taking advantage of simple additivity and site-uniformity properties of a cost model and of clever strategies that improve on the basic dynamic programming algorithm.
Abstract: A state transition model for the optimization of query processing in a distributed database system is presented. The problem is parameterized by means of a state describing the amount of processing that has been performed at each site where the database is located. A state transition occurs each time a new join or semijoin is executed. Dynamic programming is used to compute recursively the costs of the states and the globally optimal solution, taking into account communication and local processing costs. The state transition model is general enough to account for the possibility of parallel processing among the various sites, as well as for redundancy in the database. The model also permits significant reductions of the necessary computations by taking advantage of simple additivity and site-uniformity properties of a cost model, and of clever strategies that improve on the basic dynamic programming algorithm.

60 citations


Network Information
Related Topics (5)
Formal specification
18.3K papers, 370.6K citations
76% related
Model checking
16.9K papers, 451.6K citations
74% related
Software development
73.8K papers, 1.4M citations
73% related
Software construction
36.2K papers, 743.8K citations
72% related
Concurrency
13K papers, 347.1K citations
72% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20251
202426
202314,059
202232,515
2021467
2020690