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State (computer science)

About: State (computer science) is a research topic. Over the lifetime, 24436 publications have been published within this topic receiving 225733 citations.


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Journal ArticleDOI
TL;DR: Nine symmetry-related Boolean logic operations are described and experimentally demonstrated by controlling conventional Ta/TaOx/Pt memristors integrated in a crossbar array with applied voltage pulses to perform conditional SET or RESET switching involving two or three devices.
Abstract: The conditional switching of memristors to execute stateful implication logic is an example of in-memory computation to potentially provide high energy efficiency and improved computation speed by avoiding the movement of data back and forth between a processing chip and memory and/or storage. Since the first demonstration of memristor implication logic, a significant goal has been to improve the logic cascading to make it more practical. Here, we describe and experimentally demonstrate nine symmetry-related Boolean logic operations by controlling conventional Ta/TaOx/Pt memristors integrated in a crossbar array with applied voltage pulses to perform conditional SET or RESET switching involving two or three devices, i.e., a particular device is switched depending on the state of another device. We introduce a family of four stateful two-memristor logic gates along with the copy and negation operations that enable two-input-one-output complete logic. In addition, we reveal five stateful three-memristor gates that eliminate the need for a separate data copy operation, decreasing the number of steps required for a particular task. The diversity of gates made available by simply applying coordinated sequences of voltages to a memristor crossbar memory significantly improves stateful logic computing efficiency compared to similar approaches that have been proposed.

57 citations

Patent
01 Aug 2012
TL;DR: In this article, a graphical waveform showing values of one or more state variables of a computer program being debugged in two or more points in time is used to indicate a selected point in time in execution from the graphic waveform.
Abstract: A computer-implemented method, apparatus and computer program product for debugging programs, the method comprising: displaying a graphic waveform showing values of one or more state variables of a computer program being debugged in two or more points in time; receiving a user selection from points in time, of an indication to a selected point in time in execution from the graphic waveform; and resuming within a debugger an execution state of the computer program associated with the selected point in time.

57 citations

Patent
23 Aug 2001
TL;DR: In this paper, an information processing apparatus includes a controller (1) and a game machine (2) to which the controller is connected, and from at least one of a plurality of switches provided on the controller, a digital output or an analog output is obtained in accordance with an operating state of the switches thereof.
Abstract: An information processing apparatus includes a controller (1), and a game machine (2) to which the controller (1) is connected, and from at least one of a plurality of switches provided on the controller (1), a digital output or an analog output is obtained in accordance with an operating state of the switches thereof. A CPU of the game machine (2) carries out a first processing operation of game information in response to the analog output, and also carries out a second processing operation associated with the first processing operation in response to the digital output.

57 citations

Patent
31 Aug 1998
TL;DR: In this paper, a Phase Logic Module (PLM) is implemented within a programmable controller in accordance with the same state machine model so as to mirror the state machine operation of the batch server process within the programmable controllers.
Abstract: Methods and apparatus for batch process control in which a Phase Logic Module operable in accordance with the state machine model of the batch server program is embedded within a programmable controller. More specifically, a phase executed by the batch server program in a data processing device is operable in accordance with a pre-defined state machine model (typically compliant with the ISA S88.01 standard). A Phase Logic Module (PLM) is implemented within a programmable controller in accordance with the same state machine model so as to mirror the state machine operation of the batch server process within the programmable controller. The PLM is pre-implemented and standardized. Specific state logic for performing desired control in accordance with the desired batch processing is defined by a control engineer using well known languages and tools and integrated with the standard PLM state machine. These methods and structure obviate the need for the control engineer to implement customized state processing logic and the associated need to test such complex state processing logic. The PLM in the programmable controller and the phase within the batch server program communicate using a high level communication protocol to exchange state processing information. Another aspect of the invention provides for implementing a PLM in a data processing device to perform soft phase processing (a phase unrelated to process I/O equipment and rather typically related to operator interaction).

57 citations

Proceedings ArticleDOI
26 Jun 2005
TL;DR: A simple compositional program logic for an imperative extension of call-by-value PCF, built on Hoare logic and the preceding work on program logics for pure higher-order functions, is proposed.
Abstract: We propose a simple compositional program logic for an imperative extension of call-by-value PCF, built on Hoare logic and our preceding work on program logics for pure higher-order functions. A systematic use of names and operations on them allows precise and general description of complex higher-order imperative behaviour. The logic offers a foundation for general treatment of aliasing and local state on its basis, with minimal extensions. After establishing soundness, we prove that valid assertions for programs completely characterise their behaviour up to observational congruence, which is proved using a variant of finite canonical forms. The use of the logic is illustrated through reasoning examples which are hard to assert and infer using existing program logics.

57 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20251
202426
202314,059
202232,515
2021467
2020690