State (computer science)

About: State (computer science) is a research topic. Over the lifetime, 24436 publications have been published within this topic receiving 225733 citations.

Information processing system and method in which computer with high load borrows processor of computer with low load to execute process

Abstract: A method and system are disclosed in which, when the load of a processor in a given computer is high, a processor is borrowed from another computer. The computer from which the processor is borrowed is selected based on an acquired load state of the other computer, and a processor lending request is issued to the selected computer. The computer which received the processor lending request selects a processor for lending, and causes the selected processor to execute a process of the computer which issued the lending request. This distributes the load on the processor by utilizing the processor resources of other computers.

Wake up of a sleeping computer using I/O snooping and imperfect packet filtering

Abstract: A reliable and simple means to awaken sleeping computers is to maintain the network interface subsystem at full power, and to filter detected packets so that when desired packets are detected, full power is restored to the entire computer. An interface to connect a computer to a network is provided, where, the computer has a high power state and a low power state, and the computer is capable of normal operation when in the high power state, and the computer is substantially inactivated when in the low power state. A packet is received from the network. The packet is filtered by computing a hash function using at least one byte selected from the packet. A transition is initiated, responsive to a result of filtering the packet, to transition the computer from the low power state to the high power state. A mask may be used to select the at least one byte. Several bytes may be selected by the mask. A first register may be used to hold the mask. A second register may be used to hold a desired result of the hash function calculation. A result of the hash function calculation is compared with a contents of the second register to determine whether or not the result of the hash function calculation matches the contents of the second register. A perfect filtering or a second hash function filtering may be combined by AND or NOT logical operations, in making the decision whether or not to awaken the computer.

A unifying methodology for intellectual property and custom logic testing

Abstract: A novel direct access test methodology that unifies the testing of pre-designed intellectual property blocks and custom user designed logic is proposed. This methodology allows the test logic and wiring used for testing custom logic to be shared for testing intellectual property using pre-computed test vectors. It provides parallel access to storage elements and so alleviates some of the issues found in serial access scan techniques. It also provides a novel solution to the non-scan element state retention problem found in single edge-triggered clock based serial scan approaches.

Power state resynchronization

Abstract: A computer system has multiple performance states. The computer system periodically determines if the software power state maintained by power management software that represents the power state of the processor or other computer system component matches the actual power state of the processor or other computer system component. If not, the actual power state and the software power state are resynchronized, for example, by reinitializing the power management software or otherwise causing the software power state to match the hardware power state.

Plurality of distinct multiplexers that operate as a single multiplexer

Abstract: A multiplexing arrangement. The multiplexing arrangement comprises a set of data inputs wherein a first multiplexer is coupled to a first subset of the set of data inputs and a second multiplexer is coupled to a second subset of the set of data inputs. Only one of the first and second multiplexers is selected to pass one of the set of data inputs at any given time. A logic gate is coupled to the first and second data outputs, and the logic gate synthesizes an output signal for the multiplexing arrangement in response to values output by the first and second multiplexers such that the multiplexing arrangement operates as a single multiplexer. According to one embodiment, the multiplexer that is not selected to pass data has its output biased to a known state.