State (computer science)

About: State (computer science) is a research topic. Over the lifetime, 24436 publications have been published within this topic receiving 225733 citations.

Concurrent virtual machine snapshots and restore

Abstract: Various mechanisms are disclosed herein for the saving and restoring of virtual machine environment state. For example, virtual machine state can be either be saved or (multiple) snapshots can be taken of the virtual machine state. In the latter case, virtual processors can be allowed to run while the memory of the virtual machine state is being saved. In either case, virtual devices associated with the virtual machine environment can be quiesced such that these devices can prepare themselves to be saved. Once such virtual devices and memory are saved, they can also be restored. For example, restoration of memory can occur while virtual processors are running at the same time. And, moreover, restoration can occur in batches of pages, thus optimizing the response time for restoring saved data.

Predicate Abstraction with Indexed Predicates

Abstract: Predicate abstraction provides a powerful tool for verifying properties of infinite-state systems using a combination of a decision procedure for a subset of first-order logic and symbolic methods originally developed for finite-state model checking. We consider models containing first-order state variables, where the system state includes mutable functions and predicates. Such a model can describe systems containing arbitrarily large memories, buffers, and arrays of identical processes. We describe a form of predicate abstraction that constructs a formula over a set of universally quantified variables to describe invariant properties of the first-order state variables. We provide a formal justification of the soundness of our approach and describe how it has been used to verify several hardware and software designs, including a directory-based cache coherence protocol.

Portable computer system with an operating system-independent digital data player

Abstract: A portable computer system provides an operating system-independent digital data player. The computer system includes an operating system, a data storage medium to store a plurality of digitally encoded data files, and a digital data player to decode and play the plurality of digitally encoded data files in an operating system-independent digital data mode. The data storage medium may be any of the storage media for the computer system such as a hard disk drive, a CD-ROM drive, a DVD drive or removable data storage. A mini-display panel of the portable computer system displays control status information associated with playing of the plurality of digitally encoded data files in the digital data mode. The computer system further includes a digital data button to place the portable computer system in the digital data mode and a plurality of digital data control buttons to select a plurality of digital data control commands for the plurality of digitally encoded data files. Selective portions of the portable computer system are placed in a reduced power state for the digital data mode.

Method and apparatus for handling system management interrupts (SMI) as well as, ordinary interrupts of peripherals such as PCMCIA cards

Abstract: An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit (1620, 1630) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate (2672) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate (2672) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN). A second integrated circuit (110) has a system management interrupt (SMI#) output pin and SMI circuitry (2370) including a SMI register (2610) connected to events sources eligible for SMI response including the card SMI output of the first integrated circuit. This second IC (110) further has a mask SMI register (2620) connected to the SMI register (2610) to select particular ones of the events sources for SMI response. A logic circuit (2634, 2638) is fed by the SMI register (2610) for combining the selected events sources to supply an internal SMI output (SMIOUT). Other circuits, systems and methods are also disclosed.

Integrated circuit design for handling of system management interrupts (SMI)

Abstract: An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit (1620, 1630) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate (2672) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate (2672) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN). A second integrated circuit (110) has a system management interrupt (SMI#) output pin and SMI circuitry (2370) including a SMI register (2610) connected to events sources eligible for SMI response including the card SMI output of the first integrated circuit. This second IC (110) further has a mask SMI register (2620) connected to the SMI register (2610) to select particular ones of the events sources for SMI response. A logic circuit (2634, 2638) is fed by the SMI register (2610) for combining the selected events sources to supply an internal SMI output (SMIOUT). Other circuits, systems and methods are also disclosed.