State (computer science)

About: State (computer science) is a research topic. Over the lifetime, 24436 publications have been published within this topic receiving 225733 citations.

Electric socket control device

Abstract: An apparatus that controls electrical power comprising: one or more monitors adapted to sense a state of current flow supplied to a device, one or more controlled sockets, a power input; and a logic circuit The logic circuit controls electrical power to at least one of the controlled sockets responsive to the sensed state of current flow

State detecting system and device employing the same

Abstract: A state detecting system which can detect state of power storage at high precision even with lesser characteristic data to be used for calculation, and a device employing the same. The state detecting system has a memory for storing a characteristic data, calculation information, and set information, an arithmetic unit for calculating state information indicative of state of said power storage and calculating correction information for performing correction, a first correcting unit for correcting input of said arithmetic means, and a second correcting unit for correcting information stored or set in the storage.

A high I/O reconfigurable crossbar switch

Abstract: A crossbar switch with 928 inputs and 928 outputs is presented. Switching elements are constructed using logic in the routing fabric. This approach yields a 16/spl times/ improvement in logic density compared with using conventional logic. Normally, the routing is fixed. However, in FPGAs (field programmable gate arrays), the interconnection is defined by the state of SRAM configuration cells, which are dynamically modifiable. Therefore, the switch is implemented on an FPGA using partial configuration to modify routing resources during operation. All paths are synchronously clocked at 155.5 MHz, creating a total throughput of 144.3 Gbits/s. to maintain constant clock latency across all paths, partially configurable delay registers are used. Finally, the partial reconfiguration controller is implemented in hardware to enable fast switch updates.

State machine compression

Abstract: Compressing state transition instructions may achieve a reduction in the binary instruction footprint of a state machine. In certain embodiments, the compressed state transition instructions are used by state machine engines that use one or more caches in order to increase the speed at which the state machine engine can execute a state machine. In addition to reducing the instruction footprint, the use of compressed state transition instructions as discussed herein may also increase the cache hit rate of a cache-based state machine engine, resulting in an increase in performance.