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State (computer science)

About: State (computer science) is a research topic. Over the lifetime, 24436 publications have been published within this topic receiving 225733 citations.


Papers
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Journal ArticleDOI
TL;DR: An approach based on an evolutionary algorithm to design synchronous sequential logic circuits with minimum number of logic gates is suggested and the obtained results compare favourably against those produced by manual methods and other methods based on heuristic techniques.
Abstract: In this paper an approach based on an evolutionary algorithm to design synchronous sequential logic circuits with minimum number of logic gates is suggested. The proposed method consists of four main stages. The first stage is concerned with the use of genetic algorithms (GA) for the state assignment problem to compute optimal binary codes for each symbolic state and construct the state transition table of finite state machine (FSM). The second stage defines the subcircuits required to achieve the desired functionality. The third stage evaluates the subcircuits using extrinsic Evolvable Hardware (EHW). During the fourth stage, the final circuit is assembled. The obtained results compare favourably against those produced by manual methods and other methods based on heuristic techniques.

45 citations

Patent
24 Dec 1996
TL;DR: In this paper, the authors proposed a method for protecting executable computer programs against infection by a computer virus program, which prevents writing operations that attempt to modify portions of the program, such as the program's entry point or first instructions.
Abstract: A method is disclosed for protecting executable computer programs against infection by a computer virus program. The invented method prevents writing operations that attempt to modify portions of the program, such as the program's entry point or first instructions. A writing operation that attempts to write data to the program is intercepted and analyzed before the operation is allowed to be processed. The method selects significant data and stores the data, in order to retain information indicative of the program prior to any modification thereof. The invented method then determines if the writing operation is attempting to modify the significant data, and if it is determined that the writing operation is attempting to modify the data, an alarm is generated and operation is denied. If it is determined that the writing operation is not attempting to modify the data, the writing operation is allowed to continue. Additionally, the program can be restored to its initial state using the stored information and data. The method of the present invention uses the stored data indicative of the significant data of the program to restore the program to its initial state and undo all the modifications that the virus may have made to the program.

45 citations

Journal ArticleDOI
TL;DR: It is shown that a finite-state machine, whose state encoding is obtained only to reduce the amount of logic in the final implementation, may not be initializable by a logic simulator or a test generator even when the circuit is functionally initializable.
Abstract: It is shown that a finite-state machine, whose state encoding is obtained only to reduce the amount of logic in the final implementation, may not be initializable by a logic simulator or a test generator even when the circuit is functionally initializable (i.e. has synchronizing sequences). A fault simulator or a sequential circuit test generator that assumes all memory elements initially to be in the unknown state will be totally ineffective for such a design. Proper consideration for initializability during state assignment and logic optimization can guarantee the success for gate-level analysis tools. The conditions for initializability of finite-state machines are derived, and an automatic state assignment algorithm for logic minimality and initializability is given. Experimental results show that, in most cases, this method does not require more hardware than the other methods that may produce an uninitializable design. A partial reset technique, recommended for machines without a synchronizing sequence, is also discussed. >

45 citations

Journal ArticleDOI
TL;DR: The logical underpinnings of higher-order, security-typed languages with mutable state are explored, based on a logic of information flow derived from lax logic and the monadic metalanguage, employing an “informativeness” judgment indicating under what circumstances a type carries useful information.
Abstract: We explore the logical underpinnings of higher-order, security-typed languages with mutable state. Our analysis is based on a logic of information flow derived from lax logic and the monadic metalanguage. Thus, our logic deals with mutation explicitly, with impurity reflected in the types, in contrast to most higher-order security-typed languages, which deal with mutation implicitly via side-effects. More importantly, we also take a store-oriented view of security, wherein security levels are associated with elements of the mutable store. This view matches closely with the operational semantics of low-level imperative languages where information flow is expressed by operations on the store. An interesting feature of our analysis lies in its treatment of upcalls (low-security computations that include high-security ones), employing an “informativeness” judgment indicating under what circumstances a type carries useful information.

45 citations

Patent
25 Apr 2000
TL;DR: In this article, an RF transmitter capable of transmitting a plurality of different codes at different frequencies at a plurality-of-inputs (MIMO) is presented, where the controller is capable of using one pin as both an input port and output port and determines the state of various inputs by detecting changes to the I/O pin.
Abstract: An RF transmitter capable of transmitting a plurality of different codes at a plurality of different frequencies is set forth herein. The transmitter offers a new way of multiplexing inputs so that fewer controller I/O ports are needed to read or determine the state of a plurality of inputs. More particularly, the controller is capable of using one pin as both an input port and output port and determines the state of various inputs by detecting changes to the I/O pin. The multiple inputs connected to the controller pin are also connected to a pull down resistor and capacitor, and the controller can determine what state the inputs are in by detecting whether the pin input is at a logic high, low, or some state in between.

45 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20251
202426
202314,059
202232,515
2021467
2020690