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State (computer science)

About: State (computer science) is a research topic. Over the lifetime, 24436 publications have been published within this topic receiving 225733 citations.


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Patent
15 Jul 1988
TL;DR: In this article, a real-time, high uptime transaction processing system includes many user terminals communicating with service providers via a communications network and a defective logic board is replaced or a board providing system expansion is installed without powering down the system by providing external auxiliary voltages and a reset signal to the board to put it in a passive state while it is being plugged into or unplugged from its backplane connector.
Abstract: A real-time, high uptime transaction processing system includes many user terminals communicating with service providers via a communications network. A defective logic board is replaced or a board providing system expansion is installed without powering down the system by providing external auxiliary voltages and a reset signal to the board to put it in a passive state while it is being plugged into or unplugged from its backplane connector. Also under computer control the system is made inactive for a short period of time.

143 citations

Proceedings ArticleDOI
21 Jan 2009
TL;DR: LRG, a new Rely-Guarantee-based logic that brings local reasoning and information hiding to concurrency verification, supports a frame rule over rely/guarantee conditions so that specifications of program modules only need to talk about the resources used locally, and the verified modules can be reused in different threads without redoing the proof.
Abstract: Rely-Guarantee reasoning is a well-known method for verification of shared-variable concurrent programs. However, it is difficult for users to define rely/guarantee conditions, which specify threads' behaviors over the whole program state. Recent efforts to combine Separation Logic with Rely-Guarantee reasoning have made it possible to hide thread-local resources, but the shared resources still need to be globally known and specified. This greatly limits the reuse of verified program modules.In this paper, we propose LRG, a new Rely-Guarantee-based logic that brings local reasoning and information hiding to concurrency verification. Our logic, for the first time, supports a frame rule over rely/guarantee conditions so that specifications of program modules only need to talk about the resources used locally, and the verified modules can be reused in different threads without redoing the proof. Moreover, we introduce a new hiding rule to hide the resources shared by a subset of threads from the rest in the system. The support of information hiding not only improves the modularity of Rely-Guarantee reasoning, but also enables the sharing of dynamically allocated resources, which requires adjustment of rely/guarantee conditions.

143 citations

Journal ArticleDOI
TL;DR: A system developed to synthesize both finite state machines and combinational logic for low-power applications, called SYCLOP, is described, which tries to minimize the transition density at the internal nodes of a circuit to minimize power dissipation during normal operation.
Abstract: A system developed to synthesize both finite state machines and combinational logic for low-power applications, called SYCLOP, is described. SYCLOP tries to minimize the transition density at the internal nodes of a circuit to minimize power dissipation during normal operation. As input signal probabilities and transition densities are considered during the synthesis process, a particular circuit can be synthesized in different ways for different applications that require different types of inputs. For the present state inputs to the combinational circuit of a state machine, simulation was used to determine the signal probabilities and transition densities. The algorithm is not limited by the number of bits used for state assignment. The multilevel optimization process extracts kernels so that there is a balance between area and power optimization. Results have been obtained for a wide range of MCNC benchmark examples. >

143 citations

Proceedings ArticleDOI
01 Dec 1987
TL;DR: A linear algorithm that determines whether the global state transition graph associated with some concurrent program satisfies a formula in the temporal logic CTL and has been used successfully to find errors in network protocols and asynchronous circuits designs.
Abstract: 1. Introduction Many distributed programs can be viewed at some level of abstraction as communicating finite state machines. The dream of somehow using this observation to automate the verification of such programs can be traced all the way back to the early papers on Petri nets in the 1960's (1131, [lS]>. The temporal logic model checking procedure of Clarke, Emerson, and Sistia (16). [7], [20]) also attempts to exploit this observation. Their algorithm determines whether the global state transition graph associated with some concurrent program satisfies a formula in the temporal logic CTL. The algorithm is linear in both the size of the global state graph and the length of the specification and has been used successfully to find errors in network protocols and asynchronous circuits designs ([4]* 191, [17D. A number of other researchers have extended the basic model checking algorithm or

143 citations

Patent
04 May 1995
TL;DR: In this article, a method and circuit programs and automatically verifies the programming of selected EEPROM cells without alternating between programming and reading modes like prior art methods and circuitry, including a programming circuit and a bit line voltage regulation circuit.
Abstract: A method and circuit programs and automatically verifies the programming of selected EEPROM cells without alternating between programming and reading modes like prior art methods and circuitry. The circuitry includes a programming circuit and a bit line voltage regulation circuit. The programming circuit further includes a novel sense amplifier which unlike prior art sense amplifiers, is operable during both cell reading and programming modes. Included in the sense amplifier are two current providing circuits. A first circuit provides current to a selected EEPROM cell which is sufficient for reading the programmed state of the cell, and a second circuit which automatically provides additional current when required, for programming the cell. The sense amplifier detects when programming of a selected EEPROM cell has completed and causes programming of that cell to be terminated. The voltage regulation circuitry regulates the bit line voltage to the selected EEPROM cell's drain electrode. The programming circuitry, including the sense amplifier, and voltage regulation circuitry are shown to be shared between a plurality of bit lines through a bit line selection circuit.

143 citations


Network Information
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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20251
202426
202314,059
202232,515
2021467
2020690