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State (computer science)

About: State (computer science) is a research topic. Over the lifetime, 24436 publications have been published within this topic receiving 225733 citations.


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Patent
05 Feb 1999
TL;DR: In this article, a technique for acquiring and accessing information from a medical implantable device is provided, where analog parameters of interest are applied to selector switches which are controlled by a logic circuit.
Abstract: A technique for acquiring and accessing information from a medical implantable device is provided. Analog waveforms of interest are sensed and processed by signal acquisition circuitry. Analog parameters of interest are applied to selector switches which are controlled by a logic circuit. The logic circuit is also coupled an A/D converter for converting the analog signals to digital values. The digital values are stored in dedicated registers and are available for telemetry to an external device upon receipt of a request or prompt signal. When a digitized value is accessed and telemetered, the control logic circuit changes the conductive state of the selector switches to apply the corresponding analog signal to the A/D converter. The resulting digital value is applied to the corresponding register to refresh the accessed and telemetered value. The technique permits the external device to request and configure the implanted device to send only digitized values of interest. The technique also makes efficient use of the A/D converter, which consumes energy only as needed to refresh the memory when digital values are accessed and telemetered.

142 citations

Patent
25 Aug 1993
TL;DR: Sequential Coherency Instruction Scheduling as discussed by the authors allows instructions to execute in an order that may differ from that sequential order, by maintaining and saving sequential flow information and completion information about the program execution.
Abstract: A computer processor employing parallelism through pipelining and/or multiple functional units improved by Sequential Coherency Instruction Scheduling and/or Sequential Coherency Exception Handling. Sequential Coherency Instruction Scheduling establishes dependencies based on the sequential order of instructions, to execute those instructions in an order that may differ from that sequential order. Instructions are permitted to execute when all needed source operands will be available by the time required by the instruction and when all logically previous reads and writes of the destination will be accomplished before the time that the instruction will overwrite the destination. Sequential Coherency Exception Handling does not use checkpointing or in-order commit. Instead it permits out-of-order execution to actually update the permanent state of the machine out-of-order. It maintains and saves, when an exception is recognized, sequential flow information and completion information about the program execution. To resume the exception causing program after the exception is handled, the saved state is used to re-establish the program flow that was determined prior to the exception and to re-establish which instructions in that flow should not be executed, because they were completed before the exception occurred.

141 citations

Patent
29 Jul 2003
TL;DR: In this article, an over-programming condition in a multistate memory cell is detected by detecting an error signal when the data contained in a multi-state memory cell are found to be overprogrammed relative to its intended programming state.
Abstract: An apparatus and method for detecting an over-programming condition in a multistate memory cell. The invention is also directed to identifying the over-programmed cells and providing an alternate location at which to write the data intended for the over-programmed cell. An over-programmed state detection circuit generates an error signal when the data contained in a multistate memory cell is found to be over-programmed relative to its intended programming (threshold voltage level) state. Upon detection of an over-programmed cell, the programming operation of the memory system is modified to discontinue further programming attempts on the cell. The over-programmed state detection circuit is also used to assist in correcting for the over-programming state, permitting the programming error to be compensated for by the memory system.

140 citations

Patent
25 Sep 1996
TL;DR: In this paper, an authoring tool comprises at least one nestable graphic state and transition machine, referred to as a "state machine", each state machine comprising one or more states and zero or more transitions, each transition interconnecting a first state, known as the "from -- state", with a second state, referred as the ''to -- state''.
Abstract: According to the invention, an authoring tool comprises at least one nestable graphic state and transition machine, hereinafter referred to as a "state machine", each state machine comprising one or more states and zero or more transitions, each transition interconnecting a first state, known as the "from -- state", with a second state, known as the "to -- state". The first and second states can be the same state or different states. For each state in the plurality of states there can be any number of transitions, including zero, emanating therefrom and directed thereto. Each state machine has a state designated as its "current state" which changes in response to users actions or other events. Each state machine also has an initial state which is the state that is designated as the current state when the multimedia title is launched. The authoring tool allows an author to view a state machine simultaneously in several different formats, providing a full view and a map view. State machines can be nested, i.e. a state machine can be contained by another state machine. Preferably, separate user and author views are provided so that an author can manipulate a multimedia product and simultaneously observe the effect such manipulation has on the multimedia product from the user's point of view. Preferably, a plurality of modes are provided, each mode being geared toward particular functionality within the invention and a mechanism is provided so that a user of the invention can selectively switch between modes.

140 citations

Patent
Ken Reneris1
21 Sep 1998
TL;DR: In this paper, the hibernate/awake function is used to save the processor state and the executable memory state to the secondary storage prior to a computer power-down and subsequently restore the processor states and the execution state from the secondary memory after the computer powerdown without rebooting the operating system.
Abstract: A computer in accordance with the invention includes volatile executable memory and non-volatile secondary storage. An operating system is stored on the secondary storage, and is loaded into executable memory during a computer boot process. The operating system includes a hibernate/awaken function that executes from the executable memory of the computer. The hibernate/awaken function saves the processor state and the executable memory state to the secondary storage prior to a computer power-down and subsequently restores the processor state and the executable memory state from the secondary storage after the computer power-down without rebooting the operating system.

140 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20251
202426
202314,059
202232,515
2021467
2020690