State (computer science)

About: State (computer science) is a research topic. Over the lifetime, 24436 publications have been published within this topic receiving 225733 citations.

Nonvolatile semiconductor memory device

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array including regular memory cells and permanent memory cells and a control circuit. The regular memory cells are capable of switching between a first data storage state and a second data storage state. The permanent memory cells are fixed in a third data storage state that is read as the same logic level data as the first storage state. Data is stored in at least one of the regular memory cells and at least one of the permanent memory cells. The control circuit rewrites at least one of the regular memory cells from the second data storage state to the first data storage state at the time of data holding. The control circuit performs a reading operation after rewriting the regular memory cells from the first data storage state to the second data storage state.

Protocol-parsing state machine and method of using same

Abstract: A method of detecting intrusions on a computer includes storing an intrusion signature describing an attack on a computer. Once a plurality of internet protocol packets is received, the plurality of internet protocol packets collectively containing an information sequence within a series of states, it is rearranged so as to place the information sequence in order. Each state of the series of states is then successively examined so as to correlate the information sequence to the intrusion signature.

Operation scheme for programming charge trapping non-volatile memory

Abstract: A circuit and method for self-converging programming of a charge storage memory cell, such as NROM or floating gate flash. The method includes determining a data value from one of more than two data values to be stored in the memory cell, and applying a gate voltage to the control gate at one of a predetermined set of gate voltage levels selected in response to the determined data value. Programming parameters are controlled to establish a self-converging threshold state that is determined by the selected gate voltage. In this manner, the threshold voltage converges on a target threshold corresponding with the determined data value for the memory cell. Program verify operations are reduced or eliminated in various embodiments, reducing the overall time required for the program operation, and improving device performance. A second portion of the program operation can include verify operations to improve threshold margins across the array.

Framework for iterative analysis of mobile software applications

Abstract: A method is described that includes operations for receiving an application, identifying a region of interest of the application based on rules or analysis of the application, and determining specific stimuli that will cause one or more state transitions within the application to reach the region of interest. Thereafter, the stimuli is applied to the application. One or more behaviors of the application are monitored by a central intelligence engine during virtual execution of the application in response to the applied stimuli to determine whether the one or more behaviors identify that the region of interest corresponds to improperly behaving code.

Boosted supply output driver circuit for driving an all N-channel output stage

Abstract: An output driver circuit includes first and second translator circuits and a boosted voltage generator. The output driver circuit is suitable for driving the first and second inputs of a reduced voltage N-channel output stage. The first and second translator circuits each have a power terminal and an input for receiving first and second logic input signals. A boost voltage generator having a boosted voltage output is respectively coupled to the power terminals of the first and second translator circuits. The first translator circuit has an output coupled to the first input of the N-channel output stage for providing a boosted logic output signal in a logic high polarity state. The second translator circuit has an output coupled to the second input of the N-channel output stage for providing a boosted logic output signal in a logic high polarity state. The outputs of the first and second translator circuits are complementary for driving the N-channel output stage to provide a valid output logic signal. Alternatively, the outputs of the first and second translator circuits are both low for placing the N-channel output stage into a high impedance tristate mode.