State (computer science)

About: State (computer science) is a research topic. Over the lifetime, 24436 publications have been published within this topic receiving 225733 citations.

A mechanically verified language implementation

Abstract: This paper briefly describes a programming language, its implementation on a microprocessor via a compiler and link-assembler, and the mechanically checked proof of the correctness of the implementation. The programming language, called Piton, is a high-level assembly language designed for verified applications and as the target language for high-level language compilers. It provides executeonly programs, recursive subroutine call and return, stack based parameter passing, local variables, global variables and arrays, a user-visible stack for intermediate results, and seven abstract data types including integers, data addresses, program addresses and subroutine names. Piton is formally specified by an interpreter written for it in the computational logic of Boyer and Moore. Piton has been implemented on the FM8502, a general purpose microprocessor whose gate-level design has been mechanically proved to implement its machine code interpreter. The FM8502 implementation of Piton is via a function in the Boyer-Moore logic which maps a Piton initial state into an FM8502 binary core image. The compiler and link-assembler are both defined as functions in the logic. The implementation requires approximately 36K bytes and 1400 lines of prettyprinted source code in the Pure Lisp-like syntax of the logic. The implementation has been mechanically proved correct. In particular, if a Piton state can be run to completion without error, then the final values of all the global data structures can be ascertained from an inspection of an FM8502 core image obtained by running the core image produced by the compiler and link-assembler. Thus, verified Piton programs running on FM8502 can be thought of as having been verified down to the gate level.

Forward Analysis of Updatable Timed Automata

Abstract: Timed automata are a widely studied model. Its decidability has been proved using the so-called region automaton construction. This construction provides a correct abstraction for the behaviours of timed automata, but it suffers from a state explosion and is thus not used in practice. Instead, algorithms based on the notion of zones are implemented using adapted data structures like DBMs. When we focus on forward analysis algorithms, the exact computation of all the successors of the initial configurations does not always terminate. Thus, some abstractions are often used to ensure termination, among which, a widening operator on zones. In this paper, we study in detail this widening operator and the corresponding forward analysis algorithm. This algorithm is most used and implemented in tools like KRONOS and UPPAAL. One of our main results is that it is hopeless to find a forward analysis algorithm for general timed automata, that uses such a widening operator, and which is correct. This goes really against what one could think. We then study in detail this algorithm in the more general framework of updatable timed automata, a model which has been introduced as a natural syntactic extension of classical timed automata. We describe subclasses of this model for which a correct widening operator can be found.

Temporal Logic Control of Discrete-Time Piecewise Affine Systems

Abstract: We present a computational framework for automatic synthesis of a feedback control strategy for a discrete-time piecewise affine (PWA) system from a specification given as a linear temporal logic (LTL) formula over an arbitrary set of linear predicates in the system's state variables. Our approach consists of two main steps. First, by defining appropriate partitions for its state and input spaces, we construct a finite abstraction of the PWA system in the form of a control transition system. Second, by leveraging ideas and techniques from LTL model checking and Rabin games, we develop an algorithm to generate a control strategy for the finite abstraction. While provably correct and robust to state measurements and small perturbations in the applied inputs, the overall procedure is conservative and expensive. The proposed algorithms have been implemented as a software package and made available for download. Illustrative examples are included.

Test generation and verification for highly sequential circuits

Abstract: A novel test procedure that exploits the structure of the combinational logic in the circuit as well as the sequential behavior of the circuit is presented. Initially, before test generation, separate sum-of-product representations of the complete or partial ON-sets and OFF-sets of each of the flip-flop inputs and primary outputs of the sequential circuit are extracted using the PODEM algorithm. Fast algorithms for state justification and state differentiation based on this representation are described. The algorithm developed for test generation is extended to verification of finite-state machines (FSMs). The algorithm for state differentiation based on the ON- and OFF-set representation is modified for verification purposes. The authors present experimental results that illustrate the superior performance of this approach as compared to previous approaches to FSM verification. They are able to verify examples with significantly more memory elements than previous approaches. >

Non-volatile memory system having internal data verification test mode

Abstract: A memory system including means for verifying the contents of a memory cell contained in a memory array to determine if a shift in the threshold voltage level has occurred. The memory system is placed into a test mode of operation in which an internal program or erase verify operation is executed under the control of the system's internal state machine. Once in the mode, the memory system steps through each memory cell, address by address, and reads the contents of the cell using the appropriate reference voltage for a programming or erase operation. A status register bit is set indicating successful completion of the verification operation for a block of memory cells. A register bit is also set if a cell fails the verification operation. This provides a more accurate determination of the state of a memory cell than can be achieved by performing an external read operation using read operation or data verification reference voltage levels.