State (computer science)

About: State (computer science) is a research topic. Over the lifetime, 24436 publications have been published within this topic receiving 225733 citations.

Functionally Complete Boolean Logic in 1T1R Resistive Random Access Memory

Abstract: Nonvolatile stateful logic through RRAM is a promising route to build in-memory computing architecture. In this letter, a logic methodology based on 1T1R structure has been proposed to implement functionally complete Boolean logics. Arbitrary logic functions could be realized in two steps: initialization and writing. An additional read step is required to read out the logic result, which is in situ stored in the nonvolatile resistive state of the memory. Cascade problem in building larger logic circuits is also discussed. Our 1T1R logic device and operation method could be beneficial for massive integration and practical application of RRAM-based logic.

Simulation software for communications networks: the state of the art

Abstract: In the last five to ten years, simulation has been used with greater frequency to analyze communications networks, due in part to the increased number of networks in existence and to their greater complexity. The authors define the types of simulation software that are available for network analyses and also discuss desirable features for such products. They then present brief descriptions of seven prominent simulation products, emphasizing their approach to building a simulation model. They also give a four-activity approach for selecting a simulation package for an organization or a particular application. A general reference for the simulation concepts discussed in this article is Law and Kelton (1991). >

Ariadne: A Minimal Approach to State Continuity

Abstract: Protected-module architectures such as Intel SGX provide strong isolation guarantees to sensitive parts of applications while the system is up and running. Unfortunately systems in practice crash, go down for reboots or lose power at unexpected moments in time. To deal with such events, additional security measures need to be taken to guarantee that stateful modules will either recover their state from the last stored state, or fail-stop on detection of tampering with that state. More specifically, protected-module architectures need to provide a security primitive that guarantees that (1) attackers cannot present a stale state as being fresh (i.e. rollback protection), (2) once a module accepted a specific input, it will continue execution on that input or never advance, and (3) an unexpected loss of power must never leave the system in a state from which it can never resume execution (i.e. liveness guarantee). We propose Ariadne, a solution to the state-continuity problem that achieves the theoretical lower limit of requiring only a single bit flip of non-volatile memory per state update. Ariadne can be easily adapted to the platform at hand. In low-end devices where non-volatile memory may wear out quickly and the bill of materials (BOM) needs to be minimized, Ariadne can take optimal use of non-volatile memory. On SGX-enabled processors, Ariadne can be readily deployed to protect stateful modules (e.g., as used by Haven and VC3).

Multiple array customizable logic device

Abstract: Disclosed is an integrated circuit having multiple programmable arrays providing customizable logic. The integrated circuit has at least a first programmable array receiving a plurality of first inputs and generating a plurality of first outputs as programmed by the user. Also, it includes a second programmable array receiving a plurality of second inputs and generating a plurality of second outputs as programmed by the user. A means for selectiving interconnecting the inputs and outputs from the first and second programmable arrays is provided so that the programmable signals generated can be selectively connected in series, in parallel, or in a combination of series and parallel. Also provided are buried state registers for storing signals as programmed by the user. The stored signals from the buried state registers are likewise selectively interconnected with the input signals and output signals to provide added flexibility and power for the logic designer utilizing the device of the present invention.