Showing papers on "Static induction transistor published in 1977"

Voltage-controlled type oscillator

Abstract: A voltage-controlled type oscillator includes a differential amplifier constituted by a first and second transistors for establishing a current, as the collector current of the second transistor, proportional to an input control voltage, and an oscillating device for producing an oscillatory signal whose frequency is determined by that current. An element having a p-n junction is connected between the second transistor and the oscillating device and a further transistor is connected between the first transistor and a power source. A portion of the current flowing from the oscillating device is divided as a base current to the abovementioned further transistor whereby an adverse influence by the base current of the second transistor is eliminated. Thus the oscillation frequency is accurately proportional to the input control voltage.

Method of making a V-MOS field effect transistor for a dynamic memory cell having improved capacitance

Abstract: This disclosure relates to a method of making a V-MOS field effect transistor which does not require the extra steps of epitaxial growth in order to form the source area of the transistor. The formation of the source area is achieved by masking the silicon substrate, opening an aperture in the mask and then etching the silicon substrate in such a manner as to undercut the mask so that the mask provides a shield to subsequent ion implanting of the source area. Both P and N type dopants can be separately implanted with different energy levels so as to form an enhanced PN junction capacitance for the device. Such a field effect transistor can be achieved without the formation of a graded dopant concentration in the channel between the source and drain areas of the transistor and is provided with enhanced source capacitance.

Electronic switching circuit using junction type field-effect transistor

Abstract: In an electronic switching circuit using a junction type field-effect transistor, a capacitor is connected between the gate electrode of the transistor and a control pulse source. The capacitor is cooperative with a rectifying action of the gate electrode of the transistor to supply to the gate of the transistor a switching voltage which is different from the potential level of the control pulse from the control pulse source and is DC-restored following an input signal applied to the transistor.

Method of making an insulated gate field effect transistor by implanted double counterdoping

Abstract: An insulated gate field effect transistor having spaced highly doped source and drain regions with less highly doped source and drain extensions, which define the ends of the channel of the transistor, has both the source and drain extensions and the channel of the transistor defined in a controllable manner by the steps of forming a continuous zone of the same conductivity type as the source and drain regions in the space between these two regions and then counterdoping a portion of this layer.

Overvoltage protected integrated circuit network, to control current flow through resistive or inductive loads

Abstract: The main switching transistor 11 is serially connected between a load 12, 12' and a source of supply 13, R. An auxiliary transistor 15, the base of which is controlled through a voltage sensing device, for example a Zener diode 18 has its main switching path connected to the base of the main switching transistor 11 to control the main switching transistor 11 to become conductive in case of overvoltage, sensed by breakdown of the Zener diode 18. If the load is inductive, an additional inductive turn-off current bypass transistor 22, 22' can be provided (FIG. 2, 3), rendered conductive when overvoltage of an inductive kick is sensed, to bypass turn-off current around the main semiconductor switching transistor, or, in an alternative connection, to control the main switching transistor to again become conductive and itself bypass the inductive turn-off current, so that current flow due to overvoltages, or inductive turn-off current will be conducted by semiconductors operated under conditions of controlled conduction.

Bistable element and a switch circuit comprising such a bistable element

Abstract: A bistable device comprises a thyristor having anode, cathode and gate electrodes and a transistor having emitter, collector and base electrodes, the emitter-collector path of the transistor being connected to the anode-cathode path of the thyristor. A first control input is connected to the gate of the thyristor for determining one stable state of the device and a second control input is connected to the base electrode of the transistor for determining the other stable state of the device. The first control input is connected through an amplifier to the gate of the transistor.

Video amplifier with suppressed radio frequency radiation

Abstract: A wide bandwidth video amplifier suitable for driving a kinescope of a television receiver exhibits suppressed radio frequency (RF) harmonic radiation. The amplifier includes a transistor having a nonlinear conduction characteristic in a region of low current conduction. An input circuit including a source of video signals is coupled to a base electrode of the transistor, and output signals are provided from a collector output circuit of the transistor. Degenerative direct current feedback is provided from the output circuit to the input circuit. Undesired RF harmonics produced by dynamic operation of the transistor in a region of low current conduction is suppressed in a first instance by a nonlinear conduction device (e.g., a forward biased diode) arranged to provide degenerative emitter feedback for the transistor during low current conduction. Harmonic radiation is suppressed in a second instance by a low pass filter interposed between the input circuit and the base electrode of the transistor.

Static MOS memory cell using inverted N-channel field-effect transistor

Abstract: A storage cell employs two conventional N-channel MOS transistors and an inverted N-channel field-effect transistor along with an implanted polysilicon resistor and a resistor implanted under field oxide which functions as a junction field effect transistor. All of the transistors and a storage node as well as a voltage supply line are in one continuous moat region for a dense layout with a minimum of contacts. One MOS transistor is the access device connected between a bit line and the storage node with its gate connected to an address line. The other MOS transistor connects the storage node to the supply line and has its gate controlled by a second node which is connected to the supply line by a polycrystalline silicon strip which is the source-to-drain path of the inverted field-effect transistor; the gate of this device is a part of the moat which forms the storage node.

A field effect transistor logic gate having depletion mode and enhancement mode transistors

Abstract: A logic gate having a first depletion mode field effect transistor with a gate electrode adapted for coupling to a control signal source, a second depletion mode field effect transistor and an enhancement mode field effect transistor, such enhancement mode field effect transistor being serially connected to the second depletion mode transistor. The second depletion mode transistor and the enhancement field effect transistor are fed by the first depletion mode transistor. One of such serially connected transistors has a Schottky gate contact. With such arrangement the logic gate includes a "complementary" pair of relatively short channel length devices fed by a relatively short channel length device to provide low static power dissipation and large output capacitance drive capability.

High speed high voltage static induction thyristor

Abstract: We have developed a new thyristor called Static Induction Thyristor (SI Thyristor) which showed a short fall time of current (0.1 µsec) and a high forward blocking voltage (700 V). The SI thyristor has a combined structure of an N channel Static Induction Transistor and a PNP transistor. It has both capabilities of gate turn-on and gate turn-off according to the value of gate biasing voltage. We have investigated the turn-off mechanism for the high voltage device and have clarified the relation between the device parameters and carrier decaying time responsible for current fall time. From these investigation, we have improved the switching characteristics of high voltage device.

Field effect transistor having a surface channel and its method of operation

Abstract: A field effect transistor includes a semiconductor substrate of a first conductivity having a source zone and a drain zone of an opposite, second conductivity spaced apart therein and extending to the surface thereof. A surface channel adjoins the surface, is of the second conductivity, and extends in an area located between the source and drain zones. A gate electrode is carried above the surface channel, either on an insulator, or directly on the surface to form a Schottky junction. A second zone lies beneath the surface below or in overlapping relation to the surface channel and extends between the drain and source zones. The second channel is doped with dopant particles whose energy level in the forbidden band of the semiconductor substrate, at an operating temperature T, lies at a distance of more than 1/2 kT from the conduction band edge and valence band edge of the semiconductor substrate. Application of proper potentials with respect to the start voltage required for ionization of the dopant particles in the second channel causes the field effect transistor to function as a high-speed switch. Connection of the field effect transistor in series with a resistance between the poles of a power supply which has a voltage greater than the start voltage causes the field effect transistor to operate, in combination with the resistor, as an oscillator.

Gate controlled diode protection for drain of IGFET

Abstract: An integrated circuit includes an insulated-gate field effect transistor and a protection device coupled to either the source or drain of the transistor. The protection device includes a gate-controlled diode having a breakdown voltage that is less than the breakdown voltage of the drain of the field effect transistor.

Method for adjusting the leakage current of silicon-on-sapphire insulated gate field effect transistors

Abstract: A method for adjusting the leakage current of insulated gate field effect transistors comprised of silicon mesas epitaxially formed on a sapphire substrate, wherein the leakage current of a P channel transistor is increased by preoxidizing the silicon prior to standard processing and/or wherein the leakage current is decreased by annealing the silicon in a reducing atmosphere in addition to standard processing steps. The leakage current of an N channel transistor is reduced by preoxidizing the silicon of the transistor prior to forming the transistor and/or is increased by annealing in a reducing atmosphere in addition to the steps necessary for forming the transistor.

Method and apparatus for driving a transistor operated in saturation

Abstract: A method and apparatus for driving a transistor wherein a control voltage and a cut-off voltage are applied to the base of the transistor to cause the transistor to conduct current and to cut-off, respectively, and wherein, preceding the application of the cut-off voltage, a further voltage is applied to the base of the transistor for a predetermined desaturation time interval Δt which depends upon the storage or delay time of the transistor. In accord with the invention, the aforesaid further voltage corresponds to the voltage at which the current at the base of the transistor is approximately zero.

Integrated circuit protection device comprising diode having large contact area in shunt with protected bipolar transistor

Abstract: A protection device for integrated circuits used on television sets is described which protects the devices against damage of the type caused by kinescope arcing. The protection device described comprises a diode having a first region of the same conductivity type as the emitter region of the protected bipolar transistor and a second region of opposite conductivity type to the first region which second region contacts only the collector of the protected transistor. An electrode contacts the first region of the diode over a much larger area than the area the same electrode makes contact to the emitter of the protected bipolar transistor in order to allow large transient currents to go to ground through the diode rather than through the transistor thereby protecting the transistor from destruction due to transient discharges.

Field effect transistor having a linear attenuation characteristic and an improved distortion factor with multiple gate drain contacts

Abstract: A field effect transistor having two electrodes and distributed resistance therebetween is disclosed. This device is used as an attenuator when a main signal is applied across one drain electrode and a source and a control voltage is applied between a gate and the source. The output is derived from the other drain electrode.

Self-excited mixer circuit using field effect transistor

Abstract: A self-excited mixer circuit using a dual gate type field effect transistor, in which an inductive impedance element inductive with respect to a local oscillation frequency, a first capacitive element and a second capacitive element are connected across the drain and the second gate, across the drain and the source, and across the second gate and the source, respectively, of field effect transistor to constitute an oscillation circuit across the drain and the second gate of transistor, so as to derive an intermediate frequency signal from the drain of the transistor in response to the application of the radio frequency signal to the first gate of transistor.

Push-pull switching circuit with minority carrier storage delay

Abstract: A push-pull switching circuit including two grounded emitter transistors 5, 6 controlled by a pair of AND gates 3, 4. The collector output of each transistor is fed back to an input of the AND gate controlling the other transistor, the remaining AND gate inputs being supplied by the Q and Q outputs of a flip-flop circuit 2. During the prolonged conduction of each transistor due to minority carrier storage, its lowered collector potential prevents the enabled AND gate for the other transistor from raising its output and initiating conduction, thereby avoiding overlapping or simultaneous transistor conduction.

Short-channel V-groove complementary MOS device

Abstract: An improved short-channel complementary MOS transistor structure is provided. The problems of low punch-through voltage breakdown, and "short-channel effects" are particularly addressed and solved. Accurate and precise field protection of all area surrounding the channel, source and drain regions of both the p-channel MOS transistor device and the n-channel transistor device is simply and effectively accomplished. The threshold voltage of the n-channel MOS transistor device is precisely controlled by a boron implantation. The method of manufacturing such device is disclosed.

Switchable current amplifiers

Abstract: A current amplifier has its input terminal connected to the collector electrode of its master transistor by the forward-biased emitter-base junction of a complementary conductivity input transistor. This input transistor has its collector electrode connected with potential offset to the base electrode of the master transistor. The complementary conductivity transistor tends to operate in saturation, completing a collector-to-base feedback connection for the master transistor that regulates its emitter-to-base potential to its collector-to-emitter path to conduct substantially all the applied input current. A similar emitter-to-base potential is applied to a slave transistor having its collector electrode connected to the output terminal of the current amplifier and demanding a collector current as output current proportionally related to the input current. The current mirror amplifier operation is readily disabled by diverting the collector current of the input transistor away from the base electrode of the master transistor.

Single transistor memory cell employing an amorphous semiconductor threshold device

Abstract: A single transistor memory cell wherein the memory cell is provided by the base collector capacitance of the transistor in the integrated circuit chip. Mounted on top the chip in electrical contact with the base of the transistor is an amorphous semiconductor threshold device employing a tellurium based chalcogenide such that when a charge is applied to the terminal of the device opposite the transistor base, the device will be switched to a high conducting state until such time as the base collector capacitance has been charged and then the threshold device will be switched to a low-conducting state. Specifically, the amorphous threshold device employs Ge 15 Te 81 Sb 2 S 2 .

Monolithic combination of two complementary bipolar transistors

Abstract: In the production of integrated I 2 L-circuits, a lateral transistor and a vertical transistor are generated next to one another on the surface of a monocrystalline semiconductor body. Thereby, it is seen to that the base zone of the vertical transistor coincides with the collector zone of the lateral transistor and the base zone of the lateral transistor coincides with the emitter zone of the vertical transistor. Further, it is known to provide at least one collector zone of monocrystalline semiconductor material belonging to the vertical transistor and marked off from the base zone of this transistor by a pn-junction and to provide a Schottky contact as collector electrode. The invention makes provisions for applying a polycrystalline layer of the same semiconductor material and the doping of the collector zone on the surface of the monocrystalline collector zone and then making this the carrier of the collector electrode or collector electrodes, respectively. In addition to reducing the effort otherwise required, an increase of the component density as well as a series of structural improvements can be attained.

Read-out amplifier circuit for a dynamic MOS memory

Abstract: A read-out amplifier circuit for a dynamic MOS memory has two arms each of which includes a switching transistor and a load transistor connected in series, the arms being connected in parallel with a feedback connection between the junction of a switching transistor and a load transistor and the control electrode of the switching transistor of the other arm. The junctions of the switching transistors and load transistors are connected to respective sub-portions of a bit line and are also connected by way of a balance transistor. The source electrodes of the switching transistors are connected to a node which is charged prior to the beginning of a reading cycle and, for evaluating a read-out signal, is discharged in a controlled manner such that the switching transistor whose drain electrode is subjected to the voltage change which gives rise to the read-out signal is rendered conductive. Following the charging of the node, the load transistors are disconnected and the balance transistor is conductive so that the voltage existing across the node influences the junction points. Then the balance transistor is disconnected and during a subsequent evaluation of a read-out signal, the controlled discharge of the node causes the other switching transistor to temporarily pass into the conductive state.

Junction field effect transistor having unsaturated drain current characteristic with lightly doped drain region

Abstract: A field effect transistor has the property that the product of its series resistance and its true transconductance is less than one throughout the entire range of drain voltage in the operative state of the transistor, the series resistance being the sum of the resistance from source to channel and the resistance of this channel. In order to prevent an excessive increase in the active resistance of the channel, the channel is made to have an impurity concentration as low as less than 1015 atoms/cm3, preferably less than 1014 atoms/cm3, so that the depletion layers extending from the gates grow extensively to become contiguous in response to a small increase in the reverse gate voltage applied. As a result, the field effect transistor of this invention has an unsaturated drain current versus drain voltage characteristic.

Transistor having improved junction breakdown protection integrated therein

Abstract: An improved integrated transistor device has reverse bias breakdown protection for the base-collector junction. The base-collector junction is protected by means of a diode region providing a punchthrough protective mode of operation. The configuration disclosed provides a device which has comparatively stable and relatively high energy junctions therein.

Static memory cell with inverted field effect transistor

Abstract: An integrated semiconductor memory device of the static type uses a memory cell circuit having an MOS transistor of the conventional type as the access transistor, along with a resistance element buried under field oxide and an inverted field-effect transistor formed by a polycrystalline layer over a gate region. The MOS transistor connects a storage node to the access line, and the inverted field-effect transistor connects the storage node to reference potential. The storage node is connected to a second node through the resistance element, and a resistor connects the second node to a voltage supply; the magnitude of the resistance element varies according to the voltage on the storage node. The impedance of the inverted field-effect is determined by the voltage on the second node which is a moat region forming the gate.

Integrated logic - Static induction transistor logic

Abstract: SOLID-STATE CIRCUITS are designed to minimize both delay time and operational power. The product of these is thought t o be constant, represented by a specific figure for each type of integrated circuit. The 12L structure has been shown to operate with the lowest switching energy’. The power efficiency of the Vertical Injection Logic (VIL) structure shows a further improvement, by a factor of two. However, its fabrication requires the use of 7-8 masks’. A new logic circuit structure is proposed Static Induction Transistor Logic (SITL) utilizing the static induction transistor ( SIT)3. This logic circuit permits a further reduction in the power-delay time product (theoretically 6 x and experimentally, one order of magnitude). In the case of 12L, it is made by a 3 or 4-mask technology. The packing density can be as high as 1000 gates/cm2. In this logic structure, the SITS are used as the output transistors and the lateral bipolar PNP transistor is used as the injector, as usual, as shown in Figure 1. The SIT consists of Nt drains on the top surface of the Nepitaxial layer, a Pt gate configured on both sides of the drain on the same surface and the space charge layer formed surrounding the drain regions, Nchannels penetrating the gate region below the drains and the N+ source substrate. The channels are about 2-3 p m in diamcter and are formed by lateral P-type diffusion. The fabrication process in this case is as follows. The Nepitaxial layer is grown on the N+ substrate, having a carrier concentration of 2-3 x 1013 cm-3 and a thickness of 4-5 pm. After oxidation and photolithography, B-diffused layers were formed as the gate regions of the SIT and the emitter of the injector (the lateral transistor), followed by the second oxidation. Then, the Nf -diffusion layers are formed as drain regions, followed by the opening of contact holes in the Si02 film, using the third photolithography. After A1 evaporation, the A1 film is selectively etched, and the ring oscillator formed, as shown in Figure 2.

The early voltage of a bipolar transistor

Abstract: A simple concentration profile is assumed and the Early voltage of a p-n-p transistor is calculated. The base gradient, the current gain, and the collector resistivity appear as parameters in the final equation for the Early voltage. Experimental results are presented.

Protective system for power stage of monolithic circuitry

Abstract: A power transistor in the final stage of an IC amplifier feeding a reactive load, such as a loudspeaker, has an emitter resistor connected across the input of a monitoring transistor by way of a diode, the monitoring transistor being part of a protective circuit which reduces the input signal to the power amplifier in the event of an overload. To retard the response of the protective circuit, for the purpose of preventing signal distortions in the event of brief power surges, the diode and the monitoring transistor are so disposed on the silicon chip of the amplifier that a thermal wave from the overheating power transistor will first strike the diode, thereby reducing its resistance to compensate for an increased voltage drop across the emitter resistor, and will reach the monitoring transistor with a certain delay; if the overload persists, the resulting increase in the conductivity of the monitoring transistor re-establishes the full sensitivity of the protective circuit.

Static Induction Logic-A Simple Structure with Very Low Switching Energy and Very High Packing Density

Abstract: The new logic structure using static induction transistor is presented. This logic structure has very low delay-power product, and order below 0.01 pJ is possible. High current gain of presented transistor makes n-diffusion isolation layer between gates unnecessary and allows high packing dencity, higher than 1000 gate/mm22. Standard technological process requires the 4-masking steps only, however 3-mask technology is also presented.