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Showing papers on "Static induction transistor published in 1978"


Proceedings ArticleDOI
01 Jan 1978
TL;DR: In this paper, a new breakdown mechanism in a short channel MOS transistor is proposed based on experimental measurements of substrate currents, which is similar to the operation of a unijunction transistor during switching.
Abstract: In this paper a new breakdown mechanism in a short channel MOS transistor is proposed based on experimental measurements of substrate currents. We have observed a negative resistance in the substrate current followed by conductivity modulation, similar to the operation of a unijunction transistor during switching. By adding an external substrate resistance, saturation of the substrate current was observed in conjunction with the turn-on of the parasitic NPN (source-substrate-drain) bi-polar transistor. Breakdown of the device will occur when the drain bias reaches BV CEO of this parasitic bipolar transistor. The channel length dependence of the breakdown voltage of the short channel MOS transistor can then be explained by the dependence of BV CEO on the base width.

74 citations


Journal ArticleDOI
TL;DR: In this paper, the first step toward the realization of a power microwave SIT was taken by employing a distributed electrode structure and traveling-wave operation, and the Si SIT's which generate a 40-W output power at 200 MHz and 10 W at 1 GHz, with a cutoff frequency higher than 2.5 GHz, were fabricated.
Abstract: The principal operating mechanism of the static induction transistor (SIT) that shows exponential rather than the saturated I-V characteristics, is based on the static induction of both gate and drain voltages. It is known that the SIT has low noise, low distortion, and high audio-frequency power capability. The SIT is also a very promising device for high-frequency and high-power operation because of its short channel length, low gate series resistance, small gate-source capacitance, and small thermal resistance. Si SIT's which generate a 40-W output power at 200 MHz and 10 W at 1 GHz, with a cutoff frequency higher than 2.5 GHz, have been fabricated. This is the first step toward the realization of a power microwave SIT. Future developments of a higher power higher frequency SIT can be realized by employing a distributed electrode structure and traveling-wave operation.

74 citations


Journal ArticleDOI
TL;DR: In this article, the I-V characteristics of a static induction transistor (SIT) and their temperature dependence are established experimentally, and they are consistent with a major current transport mechanism of majority-carrier injection control plus the effect of series channel resistance.
Abstract: It is established experimentally that the I-V characteristics of a static induction transistor (SIT) and their temperature dependence are consistent with a major current transport mechanism of majority-carrier injection control plus the effect of series channel resistance. The I-V characteristics follow an exponential behavior in the low-current region and change to approximately a linear-or square-law relation in the high-current region where the negative feedback effect of the series channel resistance becomes pronounced. That the series channel resistance is small in the SIT and satisfies the condition that the product of series channel resistance and dc intrinsic transconductanee is less than unity is experimentally verified. The voltage amplification factor in the SIT has been confirmed to be almost constant for wide variations of drain current and ambient temperature.

61 citations


Patent
27 Jul 1978
TL;DR: In this article, an active multi-terminal switching device such as a transistor in electric series connection with a tunnel diode load discharges, or charges, the output node between tunnel diodes and transistor upon activating, or deactivating, the transistor by appropriate input signals.
Abstract: An active multi-terminal switching device such as a transistor in electric series connection with a tunnel diode load discharges, or charges, the output node between tunnel diode and transistor upon activating, or deactivating, the transistor by appropriate input signals. The negative current-voltage characteristics of the forward biased tunnel diode provides a large load resistance, and thus causes a low current level, during the stationary on-state of the transistor, but it also provides a small load resistance during most of the transient when the transistor is turned off, and thus causes a fast switching speed. A tunnel diode connected between gate and source of an enhancement mode n-channel GaAs junction field effect phototransistor enhances the recovery of the transistor after the activating light beam is switched off.

47 citations


Journal ArticleDOI
TL;DR: In this paper, the authors proposed a vertical three-terminal device design with short, wide channels; a wide, lightly doped drain region; and field terminator rings at the device perimeter.
Abstract: Analysis of fundamental MOSFET parameters predicts device limits in high-voltage high-speed operation that exceed the performance of bipolar devices. The optimization of voltage, speed, and "on" resistance parameters for power MOSFET's suggests a vertical three-terminal device design with short, wide channels; a wide, lightly doped drain region; and field terminator rings at the device perimeter. Utilizing this design philosophy, VMOS transistors have been produced with source-drain breakdown voltage greater than 450 V, and 5.5-Ω "on" resistance for 2.0-mm2active area. With a high channel width packing density design and 2.5-mm2active area, a 30-V transistor has also been produced having only 0.060-Ω "on" resistance. The breakdown voltage and "on" resistance of these devices exceed the performance of other power MOSFET's currently available. Also, the switching speed of these devices (better than 15 ns) far exceeds the performance of high-voltage bipolar transistors. Measurements of drain leakage current at 200-V drain potential show a resistance ratio R_{off}/R_{on} of approximately 1010for a 20-V variation in gate-to-source voltage.

47 citations


Patent
04 Apr 1978
TL;DR: In this paper, a static induction transistor of the type where carriers are injected from a source region to a drain region across a potential barrier induced in a current channel, and wherein the height of the potential barrier can be varied in response to a gate bias voltage applied to a transistor to thereby control the magnitude of a drain current of the transistor, is presented.
Abstract: In a static induction transistor of the type wherein carriers are injected from a source region to a drain region across a potential barrier induced in a current channel, and wherein the height of the potential barrier can be varied in response to a gate bias voltage applied to a gate to thereby control the magnitude of a drain current of the transistor. The product of the channel resistance R c and the true transconductance (G m ) of the transistor is maintained less than one and the product of the true transconductance and the series resistance R s of the transistor is maintained greater than or equal to one in the main operative state of the transistor. The series resistance R s is the sum of a resistance of the source, a resistance from the source to the current channel, and the channel resistance from the entrance of the current channel to the position of maximum value (extrema point) of the potential barrier in the current channel. This static induction transistor has the advantage that the current-voltage characteristic curve is nearly linear over a very wide range of drain current including the low drain current region.

40 citations


Proceedings ArticleDOI
01 Jan 1978
TL;DR: In this article, bipolar mode static induction transistor (BSIT) is designed as normally off device, where the channel is completely pinched off by the gate to channel built-in voltage, resulting in an appearance of potential barrier in the channel.
Abstract: Junction type static induction transistor is designed as normally-off device, called as bipolar mode static induction transistor (BSIT), where the channel is completely pinched off by the gate to channel built-in voltage, resulting in an appearance of potential barrier in the channel. Basic properties of BSIT are discussed theoretically and experimentally. Possibilities of high current and high speed switching performance of BSIT has been demonstrated experimentally by using the sample having a cell size of 800 × 520 µm2mounted in a high frequency package.

33 citations


Patent
26 May 1978
TL;DR: In this article, the stator winding of a brushless D.C. motor receives two current pulses per 360°-el. of rotor rotation, each current pulse being furnished via a respective current path.
Abstract: The stator winding of a brushless D.C. motor receives two current pulses per 360°-el. of rotor rotation, each current pulse being furnished via a respective current path. Each current path contains at least one power transistor switch having conductive and non-conductive states. These states are determined by respective driver transistor switches; when the driver transistor switch is in a high-output-impedance state the respective power transistor switch is rendered conductive, but when in the low-output-impedance state it renders the power transistor switch non-conductive. In various ways disclosed herein measures are taken to prevent the power transistor switches of both current paths from being simultaneously conductive. This may be accomplished using inherent or discrete base-emitter capacitances so connected that a power transistor switch is switched off abruptly but switches-on only after the elapse of a predetermined delay. Alternatively, the Hall voltage produced by the motor's rotor-position-sensing Hall cell may be applied to comparators such that the power transistor switches are not even commanded to conduct except during respective periods each shorter than 180°-el.

27 citations


Patent
01 Nov 1978
TL;DR: In this article, a control signal having a first predetermined magnitude in response to an analog voltage having a magnitude below a particular threshold and the control signal being above the particular threshold includes a threshold establishing circuit, a first transistor and a second transistor.
Abstract: A circuit for providing a control signal having a first predetermined magnitude in response to an analog voltage having a magnitude below a particular threshold and the control signal having a second predetermined magnitude in response to the magnitude of the analog voltage being above the particular threshold includes a threshold establishing circuit, a first transistor and a second transistor. The threshold establishing circuit receives the analog voltage and enables the first transistor to remain non-conductive until the analog voltage reaches the threshold. The second transistor is connected to the first transistor and to the analog voltage supply. The second transistor is arranged to be initially conductive as the magnitude of the analog voltage rises, and to become non-conductive in response to the first transistor being rendered conductive so that the desired control signal is developed at an output electrode of the second transistor.

24 citations


Patent
10 Jan 1978
TL;DR: In this article, a photo transistor and SCR are coupled in parallel between the d.c. terminals of a full wave rectifier and the collector of a transistor that is connected in an common emitter configuration.
Abstract: A solid state relay in which the control circuit for controlling a bidirectional conduction device (triac) includes a silicon controlled rectifier (SCR) and a photo transistor that is responsive to a light coupled control signal. Both the SCR and the photo transistor are coupled in parallel between the d.c. terminals of a full wave rectifier. The base of the photo transistor and the gate of the SCR are coupled to the collector of a transistor that is connected in an common emitter configuration between the d.c. terminals of the rectifier. The last-named transistor has its base connected to the collector of the photo transistor. The last-named transistor is a zero voltage crossover detector and conducts only when the photo transistor is nonconducting. The photo transistor and SCR may conduct only when the crossover detector transistor is nonconducting.

24 citations


Patent
Cappa Maurus1
10 Jan 1978
TL;DR: In this article, a first transistor switch connects a first voltage source to a first output terminal and a second transistor switch is connected to the control electrode of the first switch, when conducting, causes the first transistor switches to conduct.
Abstract: The present invention provides means for sequencing various supply voltages to electronic circuits and devices to thereby protect those circuits and devices from exposure to deleterious voltages. A first transistor switch connects a first voltage source to a first output terminal. A second transistor switch is connected to the control electrode of the first transistor switch. The second transistor switch, when conducting, causes the first transistor switch to conduct. The second transistor switch is turned on by a second voltage source which is connected through a delay circuit to the control electrode of the second transistor switch. The second voltage source also is connected through a diode and capacitor circuit to a second output terminal.

Patent
Merle V. Hoover1
22 May 1978
TL;DR: In this paper, a complementary or quasi-complementary Class B transistor amplifier stage, the output circuits serially connected between relatively negative and relatively positive operating supply voltages to receive direct current and are operated in push-pull with each other for signal to supply a common load from the interconnection of their output circuits, has driver circuitry including a pair of field effect transistors operated in pushing-pull to supply respective halves of the amplifier.
Abstract: A complementary or quasi-complementary Class B transistor amplifier stage, the halves of which have their output circuits serially connected between relatively negative and relatively positive operating supply voltages to receive direct current and are operated in push-pull with each other for signal to supply a common load from the interconnection of their output circuits, has driver circuitry including a pair of field effect transistors operated in push-pull to supply respective halves of the Class B transistor amplifier. A p-channel field effect transistor with source electrode connected to the relatively positive operating supply voltage drives one half of the Class B transistor amplifier stage from its drain electrode, and an n-channel field effect transistor with source electrode connected to the relatively negative operating supply voltage drives the other half of the Class B transistor amplifier stage. The field effect transistors in the driver circuitry are enhancement-mode types permitting their gate electrodes to be connected together to receive input signal potential, avoiding the need for voltage translating circuitry to secure their push-pull operation.

Journal ArticleDOI
TL;DR: In this article, the current density and temperature distribution in a bi-polar power transistor operating in the switching mode under transient conditions has been computed as a function of circuit environment.
Abstract: The current density and temperature distribution in a bi-polar power transistor operating in the switching mode under transient conditions has been computed as a function of circuit environment. A modeling was done of the turnoff of the transistor in a circuit containing resistive and inductive elements. Of particular interest was the study of the local current and temperature distribution achieved in the transistor during turnoff in a circuit with a large inductance; in the process of shutoff this inductance maintains the transistor collector current at a high value as the collector junction undergoes avalanche multiplication due to the high voltage induced across this junction by the inductive load. The length of time that the transistor remains in the high-current high-voltage mode during the turnoff transient determines the extent of current crowding and local heating in the device. The method of computation was to solve numerically the electrical carrier flow as well as Poisson's and the heat-flow equations in a two-dimensional model of an n+-p-n-n+transistor structure, as a function of time. The electrical boundary conditions on the emitter, base, and collector contacts were determined by considering the transistors interaction with its electric circuit environment. This interaction was calculated at each step in time, in an iterative fashion, as the transistor was turned off by extracting current from its base lead. The study permits the evaluation of a given bipolar transistor design with respect to current crowding, heating, and impact ionization in switching circuits containing inductive loads.

Patent
21 Jul 1978
TL;DR: In this article, a simplified temperature stabilized circuit provides a current which is proportional to a variable voltage by the use of branching transistor circuitry which fixes the voltage level of the supplied current, and controls its magnitude.
Abstract: A simplified temperature stabilized circuit provides a current which is proportional to a variable voltage by the use of branching transistor circuitry which fixes the voltage level of the supplied current, and controls its magnitude. The variable voltage is supplied through a reference resistor to the emitter of a first junction transistor having its base connected to the base of an identical junction transistor having its emitter grounded, thereby fixing the input voltage to the first transistor at a virtual ground potential. A third identical transistor has its base and emitter connected in parallel with the first transistor and carries an equal amount of current. Current derived in parallel from the first and second transistor is positively proportioned relative to the current flowing in the collector path of the third transistor by a pair of mirror-connected transistors having suitable relative areas and load resistors. The desired temperature stabilized current is applied from the bases of the mirrored transistors to the ladder network of a digital to analog converter. Two cascaded digital-to-analog circuits of this type provide a stable analog output voltage proportional to the product of the two numbers represented by the binary inputs.

Patent
29 Jun 1978
TL;DR: In this paper, a static induction transistor is split into two separate gates facing each other to cooperatively define therebetween a channel or channels of this transistor, and the non-driving gate may be held at a certain potential or floated.
Abstract: In a static induction transistor, the gate structure is split into two separate gates facing each other to cooperatively define therebetween a channel or channels of this transistor. One of these two separate gates is operative as a driving gate for driving the transistor in response to a driving signal applied thereto, while the other one is operative as a non-driving gate which has no driving signal applied. The non-driving gate may be held at a certain potential or floated. Such split-gate structure provides a higher operating speed of the transistor, and can be effectively applied to semiconductor memory devices. In such a memory device having split-gate structures, a plurality of field effect type semiconductor memory cells are formed perpendicular to a surface of a semiconductor wafer to enhance a high packing density of the memory device. Charge carriers are transported in the semiconductor bulk through channels defined by the split-gate structure, thereby enhancing a high-speed operation of the memory device.

Patent
30 Jan 1978
TL;DR: In this paper, a complementary MOS inverter includes transistors each of which has a dual gate structure with the threshold voltage of the channel nearest the drain of each transistor arranged to be lower than that of the source of each transistor.
Abstract: A complementary MOS inverter includes transistors each of which has a dual gate structure with the threshold voltage of the channel nearest the drain of each transistor arranged to be lower than that of the channel nearest the source of each transistor. This arrangement provides the cascode characteristics of dual gate structure, i.e., high breakdown voltage, high voltage gain, low drain output conductance, and relatively fast frequency response, but allows all four gate electrodes of the transistors to be connected in common, thus enabling relatively simple layout.

Patent
16 Jan 1978
TL;DR: In this article, a dynamic sense-refresh detector amplifier consisting of a cross coupled MOS transistor pair and two sets of loadrefresh circuits which each include a capacitor and three MOS transistors is used to eliminate the negative effect of threshold voltage losses on noise margin.
Abstract: A dynamic sense-refresh detector amplifier consists essentially of a cross coupled MOS transistor pair and two sets of load-refresh circuits which each include a capacitor and three MOS transistors. The load-refresh circuits eliminate the negative effect of threshold voltage losses on noise margin by allowing the memory cell from which information is read out and sensed to be refreshed to full 1 and 0 levels. A control terminal of a transistor of each load-refresh circuit is coupled to the transistor of cross coupled pair not associated with that load-refresh circuit. In addition, a voltage clamping transistor is used with each load device to further increase operating noise margins. The dynamic operation of the amplifier allows for relatively low power dissipation.

Journal ArticleDOI
TL;DR: Basic operation of a single SIT memory cell is experimentally demonstrated in this paper and described a high speed and high density dynamic RAM utilizing a static induction transistor (SIT) structure.
Abstract: Describes a high speed and high density dynamic RAM utilizing a static induction transistor (SIT) structure. The main conduction mechanism of an SIT is carrier injection control due to the potential hump at the intrinsic gate, where the potential hump is capacitively controlled by the gate and the drain voltage in a basic operation. The SIT forms a dynamic RAM memory cell if one of the drain and the source regions is set as a floating region directly connected to the storage capacitor. Basic operation of a single SIT memory cell is experimentally demonstrated in this paper.

Patent
09 Dec 1978
TL;DR: In this paper, a bipolar dynamic cell array with increased dielectric node capacitance and a method of making it is described, where a PNP transistor drives an NPN transistor so that information is stored at the base node capacitors of the PNP transistors.
Abstract: This describes a novel bipolar dynamic cell array with increased dielectric node capacitance and a method of making it. In the described cell a PNP transistor drives an NPN transistor so that information is stored at the base node capacitance of the PNP transistor. By using the PNP transistor as a read transistor and the NPN as a write transistor, the cell, when made in integrated form, utilizes the cell isolation capacitance to enhance the stored information without increasing the parasitic capacitances in the cell. This cell isolation capacitance can be enhanced by trenching between each cell in the array, oxidizing the trench walls and backfilling the trench with semiconductor material thereby obtaining greater contrast between 0 and 1 signals. This cell is especially useful in memory arrays.

Patent
04 Dec 1978
TL;DR: In this paper, a metal-oxide-semiconductor field effect device for constituting a single logic inverter stage is presented, which includes a multidrain transistor operating in enhancement mode and a load transistor.
Abstract: A metal-oxide-semiconductor field-effect device for constituting a single logic inverter stage. It includes a multidrain transistor operating in enhancement mode and a load transistor, both of monochannel metal-oxide-semiconductor structure. The inverter transistor comprises a single gate region and several drain regions. The single gate region and the single channel region of the inverter multidrain transistor are superimposed on both implantation planes separated by a thin insulating layer, entirely surround each drain region of the inverter multidrain transistor and are entirely surrounded by the single source region of the inverter multidrain transistor.

Patent
27 Mar 1978
TL;DR: In this article, a control loop consisting of a serially connected PNP transistor, a reference voltage generator, a voltage divider, and a comparator-amplifier is used to provide an error control signal.
Abstract: To permit low differences between regulated output voltage and unregulated input voltage, for example in the order of only 200mV, a control loop formed of a serially connected PNP transistor 11, a reference voltage generator 15, a voltage divider 13 connected across the regulated output, and a comparator-amplifier 14 comparing the output taken from the voltage divider 13 and the reference and providing an error control signal has a second control loop connected thereto which includes a transistor and a current sensing resistor connected to the base of the control transistor 11 and a second comparator comparing the actual current flow through the transistor 18 and the error signal to stabilize the control transistor. A switching network 16 can be additionally connected to modify or affect the error signal applied to the second control loop.

Patent
30 May 1978
TL;DR: In this article, a tristate logic buffer circuit with a phase splitter transistor and a current mirror transistor is presented, with the collector of the collector connected to the voltage supply terminal.
Abstract: A current mirror transistor is included in a tristate logic buffer circuit, with its base and emitter respectively connected to the base and emitter of the phase splitter transistor and its collector connected to the voltage supply terminal. A high resistance connected between the voltage supply terminal and the collector of the phase splitter transistor causes the circuit to consume less power when the circuit is disabled; and the current mirror transistor supplements the drive current provided by the phase splitter transistor when the circuit is not disabled.

Patent
22 Dec 1978
TL;DR: A gate turn-off device is formed by the integration of a lateral SCR and a vertical power transistor operating in parallel, with the latter carrying most of the load current whereby the former may be easily turned off which in turn terminates base drive to the transistor and thus the device is turned OFF.
Abstract: A gate turn-off device is formed by the integration of a lateral SCR and a vertical power transistor operating in parallel, with the latter carrying most of the load current whereby the former may be easily turned off which in turn terminates base drive to the transistor and thus the device is turned OFF.

Patent
05 May 1978
TL;DR: In this paper, an N-type substrate is used to prevent regenerative bipolar current flow between complementary transistors in the circuit, where the drain of the P-channel MOS transistor is connected to the drain in the N-channel transistor by a P-type well.
Abstract: The invention concerns CMOS integrated circuits including an arrangement to prevent regenerative bipolar current flow between complementary transistors in the circuit. In one particular form, the invention provides a CMOS inverter comprising an N-type substrate in which is formed a P-channel MOS transistor together with a P-type well having therein an N channel MOS transistor, the drain of the P-channel transistor being connected to the drain of the N-channel transistor, and there being disposed in the N-type substrate between the said transistors, a P-type region preferably extending to the depth of said P-type well and electrically connected to the source of the N-channel transistor. The effect of the P-type region aforesaid is to preclude the likelihood of regenerative bipolar conduction becoming established, in use of the inverter, in the substrate, which bipolar conduction might otherwise cause destruction of the CMOS circuit.

Patent
Katsuji Marumoto1, Tsutomu Ohmae1
09 Nov 1978
TL;DR: In this article, a power switching apparatus for use in the control of a D.C. motor is described, where a power transistor with its emitter-collector path connected in series with a battery is supplied from the battery through a controllable impedance element.
Abstract: A power switching apparatus for use in the control of a D.C. load such as a D.C. motor comprises a power transistor with its emitter-collector path connected in series with the D.C. motor and a battery. A base current of the power transistor is supplied from the battery through a controllable impedance element. A control unit is provided to vary the impedance of the controllable impedance element in response to the current flowing through the emitter-collector path in such a manner that the base current changes as substantially the inverse-function of a characteristic curve indicating a D.C. amplification factor versus collector current of the power switch transistor.

Patent
06 Nov 1978
TL;DR: In this paper, the bias circuit of an oscillation transistor of a piezo-electric oscillator is used to pass current from the gate to the base electrode, and a diode is connected between the gate electrode of the field effect transistor and the base electrodes with a polarity.
Abstract: A field effect transistor is used in the bias circuit of an oscillation transistor of a piezo-electric oscillator, and a diode is connected between the gate electrode of the field effect transistor and the base electrode of the oscillation transistor with a polarity to pass current from the gate electrode to the base electrode. The source electrode of the field effect transistor is connected to the base electrode of the oscillation transistor and the drain electrode of the field effect transistor is connected to a power source.

Patent
28 Nov 1978
TL;DR: In this article, a column decode circuit for a random access memory, which is comprised of a conventional transfer gate transistor, conventional driver transistors and a conventional load transistor, is presented.
Abstract: Disclosed is column decode circuit for a random access memory, which column decode circuit is comprised of a conventional transfer gate transistor, conventional driver transistors and a conventional load transistor. The column decode circuit further includes a chip enable gate transistor according to the present invention. The conventional gate transistor transfers data stored in a corresponding memory cell of the random access memory in accordance with a column address information. The column address information received by the conventional driver transistors connected in parallel causes the above gate transistor to be conductive or nonconductive. Accordingly, the conventional load transistor will apply a voltage of a particular voltage level (Vcc) from a voltage supply to the gate of the transfer gate transistor. The chip enable gate transistor, the load transistor and the parallely connected driver transistors are all connected in series. The thus connected column decode circuit has a very low power consumption and a high speed operating capability.

Patent
04 May 1978
TL;DR: In this article, an integrated semiconductor device consisting of a first and a second static induction transistor, each including a drain and a source, each having a first conductivity type, a current channel having the first conductivities type and located between the drain and the source, and a gate having a second conductivities opposite to the first one and located adjacent to the current channel was presented.
Abstract: An integrated semiconductor device comprising: a first and a second static induction transistor each including a drain and a source, each having a first conductivity type, a current channel having the first conductivity type and located between the drain and the source, and a gate having a second conductivity type opposite to the first conductivity type and located adjacent to the current channel; and a third bipolar transistor including a collector and an emitter each having the second conductivity type, and a base having the first conductivity type and located between the collector and the emitter, the collector being connected to the gates of the first and second transistors and also to the drain of the second transistor, the source of the second transistor being connected to the source of the first transistor. The second transistor is operative for suppressing the occurrence of an unrequired excessive minority carrier injection in the first transistor.

Patent
Isao Fukushima1
07 Feb 1978
TL;DR: In this article, a signal holding circuit is described in which a parallel circuit of a constant current source circuit comprising a transistor having a constant voltage supplied to a base thereof and a hold capacitor is connected to an emitter follower transistor, a first control transistor is connected between the base of the transistor of the ERS and ground, and a control pulse corresponding in time to a duration of the pulsive noise is applied to the bases of the first and second control transistors to render the first transistor conductive only during the application of the control pulse so that a charging time constant of
Abstract: A signal holding circuit is disclosed in which a parallel circuit of a constant current source circuit comprising a transistor having a constant voltage supplied to a base thereof and a hold capacitor is connected to an emitter follower transistor, a first control transistor is connected between a base of the emitter follower transistor and ground, a second control transistor is connected between the base of the transistor of the constant current source circuit and ground, and a control pulse corresponding in time to a duration of the pulsive noise is applied to the bases of the first and second control transistors to render the first and second control transistors conductive only during the application of the control pulse so that a charging time constant of the hold capacitor during the conduction of the emitter follower transistor is reduced and a discharging time constant of the hold capacitor during the cutoff of the emitter follower capacitor is increased.

Patent
06 Feb 1978
TL;DR: In this paper, a dual field effect transistor structure for reducing the effects of threshold voltage of one of the field effect transistors as reflected to a signal source device which is coupled to the source of the transistors is disclosed.
Abstract: A dual field effect transistor structure for reducing the effects of threshold voltage of one of the field effect transistors as reflected to a signal source device which is coupled thereto is disclosed. More specifically, a p-channel enhancement mode field effect transistor having a surface conduction channel and an n-channel depletion mode field effect transistor having a buried conduction channel are formed in a semiconductor structure such that both transistors have a common gate. A voltage potential is applied to the common gate to affect the first and second depletion regions in the semiconductor structure respectively associated with the enhancement mode and depletion mode transistors to render a quiescent threshold voltage of the enhancement mode transistor which is reflected to the measuring device. The semiconductor structure is initially electrically biased in conjunction with the voltage potential applied to the common gate to cause the first and second depletion regions to pinch off the buried conduction channel substantially eliminating current flow therethrough. The signal source device may be coupled to the source of the enhancement mode transistor to conduct a first current through the surface conduction channel. This first current screens the electric field lines which are produced by the voltage potential applied to the gate to cause a modulation of the first depletion region. This modulation effects a second current in the buried conduction channel of the depletion mode transistor. A resistor network which is coupled between the drain of the depletion mode transistor and the common gate is utilized to detect the second current and accordingly control the value of the gate voltage potential in a sense which causes the first and second depletion regions to substantially pinch off the buried conduction channel or reduce the second current being conducted therethrough. In this manner, the gate voltage potential is adjusted to substantially maintain the quiscent threshold voltage.