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Showing papers on "Static induction transistor published in 1980"


Patent
14 Apr 1980
TL;DR: In this article, the authors proposed means for reducing latch-back breakdown of a DMOS transistor by providing a distributed diode with a lower breakdown voltage than the DMOS to non-destructively absorb reverse transients or by providing shunt conductance means for the diffused channel region.
Abstract: Device means for reducing latch-back breakdown thus raising the reverse-biased power capability of a DMOS transistor or the like. A DMOS transistor is an MOS field effect transistor comprising a lightly-doped (usually diffused) body region formed in a drain region; a heavily-doped source region is located in the body region in proximity to the drain. Since such a device structure also exhibits substantial bipolar transistor action, it is prone to latch-back breakdown. Means for reducing latch-back breakdown include providing a distributed diode with a lower breakdown voltage than the DMOS transistor to non-destructively absorb reverse transients or by providing shunt conductance means for the diffused channel region to reduce both the voltage and the voltage gradient in the base of the parasitic bipolar device. These means may be used singly or in combination.

119 citations


Patent
11 Apr 1980
TL;DR: In this paper, a pair of N-and P-channel insulated gate field effect transistors coupled in series are used as a load transistor and a drive transistor in an inverter circuit.
Abstract: An inverter circuit comprises a pair of N- and P-channel insulated gate field effect transistors coupled in series. One of the transistors is used as a load transistor and the other is used as a drive transistor. A diode is connected between the source and gate electrodes of the load transistor in order to hold the gate voltage of the load transistor. A resistor and a capacitor (having a larger capcitance than the gate capacitance of the load transistor) is connected to the gate electrode of the load transistor. In operation, a high voltage is applied to the source electrode of the load transistor. A low-voltage pulse, having a period shorter than the RC time constant of the resistor and capacitor, is applied through the capacitor to the gate electrode of the load transistor. The gate electrode of the drive transistor is supplied with a low-voltage input signal (having a phase which is the same as and not longer than the period of the pulse applied to the capacitor). An input pulse signal may be used as the low-voltage pulse which is applied to the capacitor.

70 citations


Journal ArticleDOI
Tadahiro Ohmi1
TL;DR: In this article, a bipolar mode SIT (BSIT) was proposed to improve the switching speed of SIT in the forward gate bias operation, which is called bipolar mode BSIT, and the drain voltage for the onset of current saturation was lower than that of the bipolar transistor.
Abstract: Static induction transistor (SIT) having a short-channel structure is characterized by small gate capacitance, high transconductance, and nonsaturation current-voltage characteristic. The major mechanism of current transport in SIT is majority-carrier injection due to barrier height control at the intrinsic gate in the channel. When the channel is completely pinched off due to the gate-to-channel built-in voltage in a junction-gate SIT (JSIT), there appears a normally-off SIT. In the forward gate bias operation of JSIT, which is called bipolar mode SIT (BSIT), the switching speed is far more improved from the conventional JSIT. BSIT exhibits saturation current-voltage characteristic. In BSIT, the drain voltage for the onset of current saturation is lower than that of the bipolar transistor and the current density is very high, leading to characteristics of low impedance, high transconductance, and high current gain. Applications of SIT in LSI are discussed especially concentrating on the BSIT. SIT logic circuit (SITL) containing BSIT exhibits short propagation delay time and low power dissipation and is very promising in the future development of VLSI.

50 citations


Journal ArticleDOI
TL;DR: In this article, a 600-V vertical power MOSFET with low on-resistance is described, achieving near-ideal drain junction breakdown voltage and reduced drain spreading resistance from the use of an extended channel design.
Abstract: A 600-V vertical power MOSFET with low on-resistance is described. The low resistance is achieved by means of achieving near-ideal drain junction breakdown voltage and reduced drain spreading resistance from the use of an extended channel design. The various tradeoffs inherent in the design are discussed. Both calculated and experimental data are presented. The remote source configuration of the experimental device is also discussed.

45 citations


Patent
17 Mar 1980
TL;DR: In this paper, a back-illuminated static induction transistor (SIT) image sensor operating in the electron depletion storing mode, where the n + buried floating region 23 serves as storage region.
Abstract: This invention relates to a semiconductor image sensors and more particularly, to a back-illuminated-type static induction transistor image sensors. FIGS. 4A to 4C show the back illuminated type SIT image sensors operating in the electron depletion storing mode, where the n + buried floating region 23 serves as storage region.

39 citations



Patent
25 Jun 1980
TL;DR: In this paper, a self-contained detector-transmitter for use as a remote fire alarm is described, which consists of at least one transistor and a transformer having a high turns ratio.
Abstract: An electronic device comprises an arrangement which makes it possible to power a transmitter in self-contained fashion from a pick-up without any other power source. The device comprises at least one transistor and a transformer having a high turns ratio. The primary windings are connected in series with controlled electrodes of the transistor. The secondary windings of the transformer act on the controlling electrode of the transistor and the very low voltage is applied across the primary windings and the controlled electrodes. Voltages of a few mV which are thus applied result in the appearance of voltage pulses of a usable magnitude at the terminals of the secondary winding which may be accumulated in a capacitor to feed the transmitter intermittently. This device can be used in a self-contained detector-transmitter for use as a remote fire alarm.

29 citations


Patent
18 Aug 1980
TL;DR: In this paper, a protection circuit for a semiconductor device such as a field effect transistor is disclosed having an oscillator which is connected to both the gate turn-on circuitry and to the drain-source circuit of the FET.
Abstract: A protection circuit for a semiconductor device such as a field effect transistor is disclosed having an oscillator which is connected to both the gate turn on circuitry and to the drain-source circuit of the field effect transistor for sensing the voltage of the drain-source circuit and for turning off cyclically the field effect transistor upon the simultaneous occurrence of a gate turn on signal to the gate of the transistor and high drain-source voltage.

29 citations


Patent
11 Nov 1980
TL;DR: In this article, the authors proposed cross-coupled flip-flops with a driver and a complementary driver or load connected in series in each of the circuits, one driver or complementary driver being a floating gate transistor such as a FATMOS.
Abstract: Memory circuits having a floating gate transistor as a non-volatile storage element are constructed with a shunt transistor across the floating-gate transistor which in the event of a short circuit between the floating gate and the transistor substrate causes the memory to go into a predetermined fail-safe condition. The circuits are cross-coupled flip-flops with a driver and a complementary driver or load connected in series in each of the circuits, one driver or complementary driver or load being a floating gate transistor such as a FATMOS. Short circuiting of the floating gate to the control gate of the floating-gate transistor gives the same fail-safe condition.

25 citations


Patent
11 Jan 1980
TL;DR: In this article, a static push-pull driver circuit employs an enhancement mode input transistor and two parallel load transistors, with an input logic voltage on the gate of the input transistor.
Abstract: A static push-pull driver circuit employs an enhancement mode input transistor and two parallel load transistors, with an input logic voltage on the gate of the input transistor and its complement on the gates of the load transistors. One load transistor is a depletion mode and the other a "low-threshold" device; the threshold voltage of the low-threshold transistor is much less than that of the enhancement mode input transistor.

25 citations


Journal ArticleDOI
TL;DR: The bipolar mode SIT (BSIT) as mentioned in this paper is a normally-off device, where the channel is completely pinched off by the gate to channel built-in voltage, thus establishing a potential barrier in the channel.
Abstract: Junction gate static induction transistor (JSIT) is designed as normally-off device, where the channel is completely pinched-off by the gate to channel built-in voltage, thus establishing a potential barrier in the channel. An application of forward gate bias voltage lowers the potential barrier and allows the drain current to flow. This normally-off JSIT is called bipolar mode SIT (BSIT). Basic characteristics of BSIT is similar to that of bipolar transistor. BSIT is characterized by low impedance, high current gain, high transconductance and high current density, so that BSIT is promising for high current, high speed and high efficiency switching devices as well as low voltage and low energy integrated circuits. Basic operational principle of BSIT is described by feedback theory with a consideration to the virtual base resistance.

Patent
15 Dec 1980
TL;DR: In this article, a two transistor CMOS inverter has the two transistor gates coupled together by a coupling capacitor and D-C gate bias is supplied to each transistor through high value resistors.
Abstract: A two transistor CMOS inverter has the two transistor gates coupled together by a coupling capacitor. D-C gate bias is supplied to each transistor through high value resistors. The P-channel transistor is biased one threshold below V DD and the N-channel transistor is biased one threshold above ground. The biasing voltages are developed through the use of a current mirror so that the biasing is independent of processing variables and temperature. This form of biasing renders the circuit class B regardless of the source to drain voltage and ensures low current operation. A crystal oscillator created using such an inverter and biasing will operate at voltages substantially below sum of P and N thresholds and at a current level about one-fifth of that of a conventional CMOS oscillator.

Patent
Hitoshi Ohmichi1, Hiromu Enomoto1, Yasushi Yasuda1, Yoshiharu Mitono1, Taketo Imaizumi1 
22 Aug 1980
TL;DR: A fundamental logic circuit used, for example, in an electronic computer, comprising an output inverter transistor and a switching transistor which discharges a base charge stored in a storage capacitance in a base-emitter junction of the output inverters.
Abstract: A fundamental logic circuit used, for example, in an electronic computer, comprising an output inverter transistor and a switching transistor which discharges a base charge stored in a storage capacitance in a base-emitter junction of the output inverter transistor when the output inverter transistor changes from the turned on condition to the turned off condition.

Journal ArticleDOI
TL;DR: In this article, a new type of voltage-controlled negative-differential-resistance device using the merged integrated circuit of an n-p-n (p n-n-p) bipolar transistor and an n(p)-channel enhancement MOSFET, called the Lambda bipolar transistor, is studied both experimentally and theoretically.
Abstract: A new type of voltage-controlled negative-differential-resistance device using the merged integrated circuit of an n-p-n (p-n-p) bipolar transistor and an n(p)-channel enhancement MOSFET, which is called the Lambda bipolar transistor, is studied both experimentally and theoretically. The principal operation of the Lambda bipolar transistor is characterized by the simple circuit model and device physics. The important device properties such as the peak voltage, the peak current, the valley voltage, and the negative differential resistance, are derived in terms of the known device parameters. Comparisons between the characteristics of the fabricated devices and the theoretical model are made, which show that the analysis is in good agreement with the observed device characteristics.

Patent
20 Jun 1980
TL;DR: A field effect transistor (FE transistor) as mentioned in this paper is a semiconductor device that is composed of a semi-insulating substrate consisting of a compound semiconductor, an N type semiconductor layer formed on the substrate, a plurality of P-type semiconductor gate regions aligned along a straight line and extending through the semiconductor layers to reach the substrate to reduce dispersion in the gate pinch off voltage and can be prepared at a high yield.
Abstract: A field effect transistor device is constituted by a semiinsulating substrate consisting of a compound semiconductor, an N type semiconductor layer formed on the substrate, a plurality of P type semiconductor gate regions aligned along a straight line and extending through the semiconductor layer to reach the substrate, source and drain electrodes disposed on the semiconductor layer on the opposite sides of the drain regions, a gate electrode having an ohmic contact with the gate regions and having a Schottky contact with the semiconductor layer interposed between the gate regions. Two gate regions on the opposite ends of the array are in contact with the boundary region of the transistor. The field effect transistor device is useful for fabricating an integrated circuit and consumes less electric power. Further it reduces dispersion in the gate pinch off voltage and can be prepared at a high yield.

Patent
John D. Walker1
12 May 1980
TL;DR: A driving circuit for a power transistor switch in which a feedback transformer between the collector path of the power transistor and that of the driver transistor is used to provide a current drive to the transistor that is proportional to the load current, and a reverse current drive is applied by way of a third winding on the transformer to the emitter-base circuit of the transistor to decrease the switching-off time of that transistor as discussed by the authors.
Abstract: A driving circuit for a power transistor switch in which a feedback transformer between the collector path of the power transistor and that of the driver transistor is used to provide a current drive to the power transistor that is proportional to the load current, and in which a reverse current drive, also proportional to the load current is applied by way of a third winding on the transformer to the emitter-base circuit of the power transistor to decrease the switching-off time of that transistor.

Patent
17 Sep 1980
TL;DR: In a dynamic monolithic memory including a plurality of memory cells each of which comprises a capacitance and a switching field effect transistor, the source and drain electrodes of the transistor are connected to a data line and the capacitance, respectively.
Abstract: In a dynamic monolithic memory including a plurality of memory cells each of which comprises a capacitance and a switching field-effect transistor, the source and drain electrodes of the transistor are connected to a data line and the capacitance, respectively. Upon reading a memory cell, the transistor is switched on when difference between the data line voltage and the word line voltage applied to a gate electrode of the transistor exceeds a threshold voltage of the transistor.

Journal ArticleDOI
TL;DR: In this paper, the role of negative feedback action due to the series resistance, the minority carrier storage effect and the feedback mechanism due to virtual base resistance is discussed in a junction gate SIT and MIS SIT.
Abstract: Static induction transistor (SIT) has been demonstrated experimentally to achieve high power, high frequency and high current, high speed and high efficiency devices for analogue and switching applications. Low energy, high speed and high packing density integrated circuits are also possible. Fundamental superiorities of SIT compared with conventional FET and bipolar transistor are discussed in this manuscript to describe performances of junction gate SIT and MIS SIT. Discussions are concentrated on the role of the negative feedback action due to the series resistance, the minority carrier storage effect and the feedback mechanism due to the virtual base resistance.

Patent
22 Sep 1980
TL;DR: In this paper, a cross-coupled mode is proposed for detecting power supply variations in which a first and second transistor are connected in a cross coupled mode, and a load device is connected to each transistor and to a source of power.
Abstract: A circuit for detecting power supply variations in which a first and second transistor are connected in a cross-coupled mode. A load device is connected to each transistor and to a source of power. The loads are unbalanced such that upon application of power to the circuit a first state is always assumed. The cell is forced to its second state. A charge transfer device is connected between first and second nodes formed at the connection between the first transistor and its load and the second transistor and its load. Upon reduction of power supply voltage below that of the active node, a charge transfer takes place which allows the cell to return to its initial state. Detection of the initial state indicates loss or reduction of power has occurred.

Patent
Keming W. Yeh1
11 Dec 1980
TL;DR: In this article, a circular high voltage field effect transistor suitable for inclusion in LSI circuits, and the process for making said transistor, are described; the transistor comprises a central drain and concentric circular field plate, gate and source.
Abstract: A circular high voltage field effect transistor suitable for inclusion in LSI circuits, and the process for making said transistor, are described. The transistor comprises a central drain and concentric circular field plate, gate and source. Alternate embodiments include an intermediate gate and resistive gate. Implantation and diffusion techniques are described for producing the source and channel regions, and various device dimensions may be varied to improve either current or voltage handling capability or speed capability.

Patent
13 Jun 1980
TL;DR: In this article, the first and second voltages of reference are determined so that without any alternating input signal the current in the second and third transistors of the inverter is minimum and the equivalent resistances of the third and fourth transistors are very high.
Abstract: An amplifier includes an inverter with two transistors of complementary types. The first transistor is biased through a third transistor of the same type of conductivity by a first reference voltage, the third transistor being biased by a third voltage of reference. The second transistor is biased through a fourth transistor of the same type of conductivity by a second voltage of reference, the fourth transistor being biased by a fourth voltage of reference. The first and second voltages of reference are determined so that without any alternating input signal the current in the first and second transistors of the inverter is minimum. The third and fourth voltages of reference are determined so that the equivalent resistances of the third and fourth transistors are very high.

Patent
08 Aug 1980
TL;DR: In this paper, a method and apparatus for applying a reverse bias voltage to the base-emitter junction of a transistor, for turning off the transistor from a normal conduction state, or for connecting a relatively low impedance current path between the base and emitter electrodes, was presented.
Abstract: A method and apparatus for applying a reverse bias voltage to the base-emitter junction of a transistor, for turning off the transistor from a normal conduction state, or for connecting a relatively low impedance current path between the base and emitter electrodes for turning off the transistor from a fault conduction state.

Patent
26 Sep 1980
TL;DR: In this article, a high-density integrated circuit with a delay function and a high density integrated structure is presented. The circuit comprises a bootstrap circuit (Q16, Q17, C) operable with a drain supply voltage (V DD ) and a source supply voltage(Vss), a first transistor of enhancement type (Q28) having a drain connectable to the drain supply voltages (VDD ), a source connected to an output node (N202), and a second transistor of depletion type(Q30) having an additional drain connected to a boot node
Abstract: A digital circuit having a delay function which is operable with low power consumption and fabricated with a high-density integrated structure is disclosed. The circuit comprises a boot-strap circuit (Q16, Q17, C) operable with a drain supply voltage (V DD ) and a source supply voltage (Vss), a first transistor of enhancement type (Q28) having a drain connectable to the drain supply voltage (V DD ) and a source connected to an output node (N202), a second transistor of depletion type (Q30) having a drain connected to a boot node (N11) of the boot-strap circuit (Q16, Q17, C) whose potential is operatively raised above the drain supply voltage (V DD ) and a source connected to the gate of the first transistor (Q28), and means for controlling the second transistor (Q28).

Patent
25 Feb 1980
TL;DR: In this paper, the potential of a single ancillary transistor, or the potential difference of the emitters of two such transistors of mutually different current densities, varies as a function of temperature and is compared with a reference voltage to apply, in the event of an overload, an inhibiting signal to a driver stage for blocking or limiting the conduction of the protected component.
Abstract: To protect a discrete electronic component such as a bipolar transistor or a field-effect transistor against destructive current surges, one or two ancillary transistors are formed in the same semiconductor body which has a major portion thereof overlain by an output electrode constituting a variable-voltage terminal connected to a load. This major portion, acting as the collector of the bipolar transistor (or of two such transistors in a Darlington configuration) or as the drain of the FET to be protected, also forms the collector of each ancillary transistor whose emitter is grounded through a constant-current generator or through a resistor. The emitter potential of a single ancillary transistor, or the potential difference of the emitters of two such transistors of mutually different current densities, varies as a function of temperature and is compared with a reference voltage to apply, in the event of an overload, an inhibiting signal to a driver stage for blocking or limiting the conduction of the protected component.

Patent
Klaus Lehmann1
04 Dec 1980
TL;DR: In this paper, an electrical circuit is provided with a field effect transistor having variable source-drain resistance, and two junction transistors are connected to the gate electrode and either to the source electrode or the drain electrode.
Abstract: To provide for essentially inertia-free amplitude adjustment of video signals, an electrical circuit is provided with a field effect transistor having variable source-drain resistance. The circuit includes two junction transistors which are connected to the gate electrode of the field effect transistor and either to the source electrode or the drain electrode. One such transistor is connected as an impedance converter, and the other in grounded base configuration. By means of a variable voltage applied to a resistor is connected to the gate electrode of the field effect transistor, source-drain resistance of the field effect transistor can be varied essentially linearly.

Journal ArticleDOI
TL;DR: In this article, the design aspects of a V-groove vertical geometry power MOST (VVMOS) using a simple epitaxial-channel technology, are discussed in detail.
Abstract: The design aspects of a V-groove vertical-geometry power MOST (VVMOS) using a simple epitaxial-channel technology, are discussed in this paper. The process has several features including ease of fabrication, good threshold voltage controllability, and high breakdown voltage. Expressions for the on-resistance as a function of device parameters and for the device capacitances as a function of the geometric features of the transistor are derived. Experimental results on fabricated devices are presented.

Patent
Max E. Malchow1
24 Apr 1980
TL;DR: In this article, a common-collector-amplifier transistor is followed in direct-coupled cascade connection by a common emitter amplifier transistor, and the emitter of the common collector amplifier transistor is supplied bias current from the collector of a constant-current-generator transistor having its emitter-to-base voltage related to that of one of the transistors in the multiple-V BE supply.
Abstract: A common-collector-amplifier transistor is followed in direct-coupled cascade connection by a common-emitter amplifier transistor. A multiple-V BE supply biases the base of the common-collector-amplifier transistor respective to the emitter of the common-emitter amplifier, so the quiescent collector current of the common-emitter-amplifier transistor can be accurately defined. To improve the high-frequency response of the common-collector amplifier transistor, while preserving the capability of accurately defining the quiescent collector current of the common-emitter-amplifier transistor, the emitter of the common-collector amplifier transistor is supplied bias current from the collector of a constant-current-generator transistor having its emitter-to-base voltage related to that of one of the transistors in the multiple-V BE supply.

Patent
Raymond Sommerer1
15 Sep 1980
TL;DR: In this article, a temperature-compensated peak detector circuit with a diode-connected transistor and a second matched transistor in emitter follower configuration is presented. But the collector currents of the two transistors are at approximately equal voltages.
Abstract: A temperature-compensated peak detector circuit which includes a diode connected transistor, the base-collector junction of which is connected across an averaging circuit to a second matched transistor in emitter follower configuration. Appropriate resistances are connected to the collector of the diode connected transistor and to the emitter of the other transistor to make equal the collector currents of the two transistors. As a result, the emitters are at approximately equal voltages. Therefore the adjusted peak voltage of the signal always appears at the emitter of the second transistor regardless of changes in ambient temperature.

Patent
Roger A. Whatley1
16 Dec 1980
TL;DR: In this article, a cross-over compensation circuit develops a predetermined bias voltage on the base of the bipolar transistor relative to the voltage on output terminal, to assure a minimum level of operation when the output terminal is near the analog ground voltage.
Abstract: A driver circuit suitable for use in an operational amplifier, includes a bipolar pull-up transistor which sources current to an output terminal in proportion to an applied drive current, and an MOS pull-down transistor which sinks current from the output terminal in proportion to an applied control voltage. An MOS drive transistor provides a constant drive current for the pull-up transistor, and an MOS shunt transistor shunts the drive current away from the bipolar transistor in proportion to the control voltage. A cross-over compensation circuit develops a predetermined bias voltage on the base of the bipolar transistor relative to the voltage on the output terminal, to assure a minimum level of operation of the bipolar transistor when the output terminal is near the analog ground voltage.

Patent
11 Feb 1980
TL;DR: In this article, the authors propose a circuit for automatically and selectively refreshing a dynamic node to a desired logic level by precharging a digit line in a random access memory with a reference potential at a threshold above ground.
Abstract: Circuitry for automatically and selectively refreshing a dynamic node to a desired logic level. Nodes at ground potential are left at ground while nodes at an intermediate level are brought up to a supply voltage level. In a preferred use the dynamic node is a digit line in a random access memory. The circuitry includes a first transistor connected between the drain supply and a digit line having a gate connected to the source of a second transistor. The drain of the second transistor is connected to a clocked source of potential at least one threshold above the drain supply. The gate of the second transistor is precharged to a potential near the drain supply voltage preferrably concurrent with precharging of digit lines in the memory proper. A third transistor is connected between the gate of the second transistor and the digit line and has a gate connected to a clocked source of a reference potential between a digit line precharge level and the level of one threshold above ground. After the state of a memory cell is read out by a sense amplifier, the reference potential is applied to the gate of the third transistor to discharge the gate of the second transistor in the event that the digit line is at a low voltage. If the cell read out on the digit line was at a high potential the gate of the second transistor remains charged so that when a potential exceeding the drain voltage by at least one threshold is applied to the drain of the second transistor it is coupled through to the gate of the first transistor which in turn pulls the digit line potential to the drain supply voltage.