Showing papers on "Static induction transistor published in 1981"

Semiconductor integrated circuit device with memory MISFETS and thin and thick gate insulator MISFETS

Abstract: A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.

Ttl to cmos input buffer

Abstract: A TTL to CMOS input buffer accomplishes buffering a TTL signal to a CMOS signal without static current flow when the TTL is a logic "1" by isolating the input from an input P channel transistor and using feedback from an input N channel transistor to turn off the P channel transistor. A second P channel transistor is used to couple a positive power supply voltage to the input P channel transistor in response to an output from the N channel transistor.

Overcurrent and overtemperature protective circuit for power transistor system

Abstract: A power transistor switch is protected against thermal destruction that might be caused by accidental short circuiting of the load being switched by a protective circuit having a base-drive-removing transistor in shunt to the base-emitter junction of the power transistor; an RC circuit including a capacitor in series with a resistor connected across the power transistor with the capacitor coupled across the base-emitter junction of the base-drive-removing transistor; a forward-biased shunting transistor connected across the capacitor; a shunt-removing transistor connected across the base-emitter junction of the shunting transistor; and a turn-on transistor triggerable to the conductive state by a turn-on signal for applying base drive to the power transistor and for forward biasing the shunt removing transistor to thereby turn off the shunting transistor and permit the capacitor to charge. Excessive current flow through the power switch causing it to desaturate results in charging the capacitor and consequent turning on the base-drive-removing transistor to thereby remove base current from the power transistor and turn it off.

Methods and apparatus for microdielectrometry

Abstract: An impedance measuring apparatus having a measuring transistor with its gate electrode adapted to form a two electrode, interdigitated capacitor with the material to be measured forming the dielectric, a second reference transistor connected in differential configuration to the measuring transistor so that their drain currents are constrained to be equal, a time-varying voltage generator connected to one electrode of the interdigitated capacitor and a gain-phase meter connected to the gate of the reference transistor.

Solid state image pickup

Abstract: A Detection Matrix having elementary modules disposed in lines and in columns. Each module has a photoconductance, a thin-film MOS transistor and a storage capacitor. The gate of the transistor is connected to a line electrode. The source of the transistor is connected to a video amplifier, and the drain of the transistor is connected to one terminal of the photocapacitance and of the capacitor. The other terminal of the photoconductance of the capacitor are both connected to the line electrode following or preceding the line electrode connected to the gate of the transistor.

Battery charging circuit

Abstract: A battery charging circuit having an electromagnetic transformer with primary and secondary coils, a rectifier connected between the secondary coil and the battery, a first transistor connected in series with the primary coil and a resistor to form a circuit in parallel with a power source, the base of the first transistor being connected to the secondary coil, and a second transistor electrically connected to the base of the first transistor The first transistor has a high switching frequency, and the battery is charged with a constant reverse current during its blocking phase, regardless of the power source voltage The first transistor is protected from reverse kick-back voltage pulses induced during its blocking phase by the provision of a diode and Zener diode connected in series across the primary coil and a capacitor interposed between the secondary coil and the base of the first transistor

Effects of drift region parameters on the static properties of power LDMOST

Abstract: The effects of the drift region geometry and the physical parameters on the thin layer (resurfed) lateral DMOS transistor operation have been studied for both the static on-state and the off-state. The variations of breakdown voltage with drift region parameters were investigated using numerical modeling and compared to the experimental results. The operation of the LDMOST in the on-channel condition was modeled semi-empirically. The analytical and experimental results show that the operation of the device depends strongly on the geometry and the physical parameters of the drift region, particularly at high gate voltages and low drain voltages. Design guidelines for the lateral DMOS transistor for switching applications are discussed.

Semiconductor integrated circuit device with low power consumption in a standby mode using an on-chip substrate bias generator

Abstract: A mode switching transistor which is controlled by a chip enable signal is connected between a power supply terminal and a MOS inverter including transistors. The transistor functions as a weak depletion or depletion type MOS transistor to provide sufficient current with a first back gate bias given in an active mode and functions as a perfect enhancement type transistor to completely cut off current with a second back gate bias given in a standby mode.

Semiconductor memory circuit with depletion data transfer transistor

Abstract: A read only memory (ROM) circuit (10) includes a memory storage transistor (16) which is fabricated to have one of a plurality of threshold voltages corresponding to predetermined data states. The source and drain terminals of the memory transistor (16) are connected between a column node (18) and a bit line (20). A lightly depleted data transfer transistor (30) is connected between the bit line (20) and a data line (14). The column node (18), bit line (20) and data line (14) are precharged. A memory address is decoded to drive a selected word line (12) and a selected column decode line (32) to a high voltage state. A transistor (34) discharges the column node (18). Depending upon the state of the memory storage transistor (16) the bit line (20) is discharged or maintained precharged. The state of bit line (20) is transmitted through the data transfer transistor (30) to the data line (14). The data transfer transistor ( 30) can be fabricated as a relatively small device due to the large turn on voltage applied thereto because the transistor (30) is a depletion device. The smaller size of a plurality of the transistors (30) results in a substantial saving in space and reduces capacitive loading on the data line (14) thereby speeding up the discharge rate of the data line (14).

High performance submicron metal-oxide-semiconductor field effect transistor device structure

Abstract: A novel metal-oxide-semiconductor (MOS) field effect transistor having enhanced oxide thickness at the edge of the gate electrode and having metal silicide regions in the gate electrode and source and drain areas. The enhanced oxide thickness improves interconnect-to-interconnect breakdown voltage in multilevel interconnect devices as well as minimizing gate overlap of source and drain. The metal silicide regions reduce series resistance and improve device speed and packing density.

Method for programming circuit elements in integrated circuits

Abstract: A laser programmable logic switch (22) includes a fusible link (28), an output node (26) and a transistor (24) which is fabricated to be in the off state. When it is desired to have the output node (26) at a low logic state, the circuit (22) is left unchanged. But if it is determined that the output node (26) should be at a high logic level state, the fusible link (28) is opened by a first laser pulse. A second laser pulse is then applied to transistor (24) to cause damage to the structure of the transistor (24). The transistor (24) can be damaged in any of a number of modes which result in the formation of a conducting path between the output node (26) and the power terminal V cc . Unlike conventional laser switch circuits, the circuit (22) does not draw static power under any conditions thereby reducing power consumption by the integrated circuit utilizing such a laser switched gate. In a further embodiment a single transistor (90) fabricated in a nonconducting state is connected between first and second nodes (92, 94) but when damaged by a laser pulse the transistor (90) provides a low impedance connection between the nodes (92, 94). In a still further embodiment a transfer (110) is provided with a fusible link gate (110a), and is fabricated to be in an off state. A laser beam programs the transistor (110) by simultaneously opening the fusible link gate (110a) and altering the structure of the transistor to provide a low impedance path between the drain and source terminals thereof.

Fast switching field effect transistor driver circuit

Abstract: A high frequency inverter power supply having isolation between the drive circuitry and the Power Switching device and utilizing a Field Effect Transistor as the Power Switching device is described. Circuitry for rapidly charging the gate capacitance of the Field Effect Transistor for enhancing the rate of its switching to the conductive state and for rapidly discharging the gate capacitance for enhancing the rate of its switching to the non-conductive state is shown.

Semiconductor image sensor

Abstract: A semiconductor image sensor which has photocells arranged in a matrix form is miniaturized and integrated with high density, thereby to increase its light amplification factor and operating speed. To this end, each photocell is formed by a static induction transistor which has a pair of main electrodes, a channel region formed between the main electrodes and a capacitor connected between a control region serving as a photocell and one of the row lines.

Circuit including an mos transistor whose gate is protected from oxide rupture

Abstract: A protected MOS transistor circuit includes an input MOS transistor and a depletion mode MOS transistor having a drain-source current path connected between ground and the gate of the input MOS transistor of obviating rupture of the gate oxide of the input MOS transistor when power is off. The depletion mode MOS transistor's gate receives a control signal only when power is on which renders the depletion mode MOS transistor nonconductive when power is on. The depletion mode MOS transistor is conductive when power is off.

Current limiting MOS transistor driver circuit

Abstract: A current limiting driver circuit (10) receives a first logic level input signal (φ 1 ) and drives an output pin (26). A node (14) is pulled to ground by a pull-down transistor (16) which receives the first input signal (φ 1 ) and is driven to a high voltage state by a pull-up transistor (12). A driver transistor (28) is turned on by a high voltage state at the node (14) and is turned off by a low voltage state at the node (14). The driver transistor (28) is connected to provide a high voltage state to the output pin (26). A pull-down transistor (30) is connected to receive the first input signal (φ 1 ) in order to pull the output pin (26) to ground. A series of transistors (18, 20, 22) are connected between the gate and source terminals of the driver transistor (28) such that when the gate-to-source voltage of the driver transistor (28) exceeds the combined thresholds of the three transistors (18, 20, 22) they will be turned on and thereby limit the maximum gate-to-source voltage of driver transistor (28). This in turn serves to limit the maximum current flow through the driver transistor (28). Disabling transistors (17, 32) are included for providing a high impedance output to the output pin (26).

Power static induction transistor fabrication

Abstract: A method for fabricating a gate-source structure for a recessed-gate static induction transistor. The method is characterized by use of doped polysilicon to fill the recessed gate grooves after the gate grooves have been etched and diffused. The gate grooves have depth greater than width and therefore the surface of the polysilicon layer deposit is substantially planar. The planar surface allows photolithographic techniques to be used for formation of gate contact regions and for depositing of metal gate and source electrodes.

Semiconductor device design and process

Abstract: A method for fabricating a gate-source structure for a recessed-gate static induction transistor. Source impurities are implanted prior to forming the recessed gates. The recessed gates are formed by a first isotropic etching step and a second anisotropic etching step which results in a unique overhanging protective layer used to protect the walls of the grooves during implantation of gate impurities in the bottom of the grooves. Implantations are driven and activated to form gate and source regions, the protective layer is removed and metal deposited to form electrodes. The procedure minimizes the required number of masking steps and associated mask registration problems.

Voltage current converter circuit

Abstract: A linear voltage-current converter circuit having a simplified circuit structure and operable over a wide voltage range is disclosed. The circuit comprises a first transistor having a drain connected to a power voltage through a first load element, a second and a third transistor having drains connected to the power voltage through a second load element, means for supplying gates of the first and second transistor with voltage signal, means responsive to a voltage difference at drains of the first and second transistors for controlling a gate voltage of the third transistor so as to reduce the voltage difference to zero, an output transistor, and means for supplying a gate of the output transistor with the same voltage as the gate voltage of the third transistor.

MOS Transistor circuit with a power-down function

Abstract: An MOS transistor circuit contains at least one "zero" threshold mode transistor to provide a power-down function for the circuit. The "zero" threshold mode transistor is connected between an enhancement-mode MOS driver transistor and a depletion-mode MOS load transistor.

A thin-film transistor for flat planel displays

Abstract: This paper reports the measured results of a thin-film transistor (TFT) for the flat panel display application. The TFT has a double-gate structure and uses a very thin (80-100 A) CdSe film as the semiconductor. The device has less than 10-10-A zero-gate-bias leakage current and greater than 106ON/OFF current ratio. It has been found that the only severe stability requirement on the device is in the OFF condition, Both dc and dynamic life tests have been made. The device performs better in the multiplexed condition than in the dc condition. Excellent maintenance of device parameters has been observed.

Multimode base drive circuit for power switching transistor

Abstract: A base drive circuit for a power switching transistor in a power inverter circuit utilizes a center tapped current transformer winding to regeneratively couple the collector current of the power switching transistor to its base drive electrode. A first segment of the center tapped transformer winding is coupled via a control transistor to provide proportional base drive to the power transistors when it is biased into conduction. This forward drive mode continues until the control transistor is biased nonconducting, at which point, the second segment of the center tapped transformer winding is connected to the base drive electrode to provide a reverse drive current to the power transistor base to provide rapid turn-off and reset the transformer. A supplemental drive path coupled to a converter power source via a diode to the control transistor operates to supply additional drive current therethrough to the power transistor at the turn-on transition in order to eliminate the quasi-saturation region that normally exists in a regeneratively driven power switching transistor at turn-on.

Speed control apparatus for direct current motor

Abstract: A speed control apparatus for a direct current motor comprises a bridge circuit having an armature in one side thereof, a direct current voltage source, and a series connection of a switching transistor and an inductor inserted between the direct current voltage source and the bridge circuit. A detecting transistor detects an unbalanced voltage of the bridge circuit and control transistors are responsive to the detection to control the switching transistor to be turned on or off. The inductor stores a magnetic energy when the switching transistor is turned on and supplies an electromotive force induced by the stored magnetic energy to the bridge circuit when the switching transistor is turned off. To that end, a diode or a transistor cooperates with the inductor and the bridge circuit to constitute a closed loop. A capacitor is connected in parallel with the armature, thereby to restrict the operation of the detecting transistor and thus the on/off-period of the switching transistor.

Transistor fault indicator

Abstract: A transistor fault indicator circuit (48, 50, 58, 60) monitors the conduction state of a transistor (34) and compares that state to a commanded state. Differences in states are treated as faults and actuate an alarm of shut down the system including the transistor (34). In systems in which the transistor (34) may be operated in a continuous conduction mode for long time periods, a control circuit is provided to periodically short circuit the base-emitter bias of the transistor (34) to force a momentary period of nonconduc- tion during which time the proper operation of the transistor (34) can be verified.

Battery charging circuit for maintaining a substantially constant average value of charging current despite variations in charging voltage

Abstract: A battery charger includes a transistor inverter. The transistor inverter includes an oscillation transformer and a switching transistor for controlling a current flowing through a primary coil of the oscillation transformer. This current charges the battery when the transistor is on. While the switching transistor is in an off state, charging current is supplied to the battery from a secondary coil of the oscillation transformer. The period of time where the switching transistor is in an on state is controlled depending on the amplitude of a supply voltage. Accordingly, the average value of a charging current to the rechargeable battery is automatically kept substantially constant despite variations in the amplitude of the alternating current voltage supply.

Method of fabricating a bipolar dynamic memory cell

Abstract: This describes a novel bipolar dynamic cell array with increased dielectric node capacitance and a method of making it. In the described cell a PNP transistor drives an NPN transistor so that information is stored at the base node capacitance of the PNP transistor. By using the PNP transistor as a read transistor and the NPN as a write transistor, the cell, when made in integrated form, utilizes the cell isolation capacitance to enhance the stored information without increasing the parasitic capacitances in the cell. This cell isolation capacitance can be enhanced by trenching between each cell in the array, oxidizing the trench walls and backfilling the trench with semiconductor material thereby obtaining greater contrast between 0 and 1 signals. This cell is especially useful in memory arrays.

Non-epitaxial static induction transistor processing

Abstract: A method for fabricating a static induction transistor starting with a high resistivity substrate on which a gate-source structure is formed. The gate-source structure is covered by a supporting layer and the wafer is etched to desired thickness. Ions are implanted in the etched surface and a drain electrode is deposited. A thick metal support layer and heat sink is electroplated on the drain electrode.

Input protection circuit for an mis transistor

Abstract: The input protection circuit protects a MIS transistor Q 0 from high voltages. Resistors R 1 and R 2 are connected in series between an input terminal in and the gate of the transistor Q o . A first protection transistor is connected between a point N1, where R 1 and R 2 are joined, and a ground power supply line V ss . A second protection transistor is connected between a point N2, where the resistor R 2 and the gate of transistor 0 0 are connected, and the high power supply line V cc . The second protection transistor Q 2 has a break-down voltage lower than the breakdown voltage of the MIS transistor Q 0 but has a high impedance when it is turned ON when a high voltage is applied to the input terminal in. The first protection transistor Q 1 has a breakdown voltage higher than that of the transistor Q o but has a low impedance when turned ON when a high voltage is applied to the input terminal in. The combination of protection transistor Q, and Q 2 provides adequate protection for the transistor Q o even when it has only a minute and very thin gate insulating film.

Solid state area imaging apparatus having a charge transfer arrangement

Abstract: A solid state area imaging apparatus having a photosensor matrix array disposed at a front surface area of a substrate and having a charge transfer arrangement for transferring charges generated in the photosensors of the matrix so as to convert them into a serial signal. It also includes a penetrative charge transfer arrangement for transferring the charge from the front surface area of the substrate to the back surface area of the substrate, and which has a static induction transistor structure. The charges are transferred vertically through a channel formed in the structure of the static induction transistor. This penetrative charge transfer arrangement may be used as a part of the transfer path for generating the serial signal or a path for removing excess charges which are generated in the photosensors.

Transistor turn off current sensing circuit

Abstract: A transistor current sensing circuit is provided for a power output transistor whose drive circuit includes a current controlled feedback transformer that has a current limited direct current source connected to the secondary winding of the transformer wherein the change in voltage level of the secondary winding upon the completion of turn-off of the output transistor is used as a signal to initiate turn-on of another associated transistor.

Negative resistance device

Abstract: A negative resistance device utilizing a substrate bias effect is comprised of two MOS transistors of n-channel type and p-channel type. The two transistors are connected at the sources and the gates. The drain of the n-channel MOS transistor is connected to the substrate of the p-channel MOS transistor. The drain of the p-channel MOS transistor is connected to the substrate of the n-channel MOS transistor.