Showing papers on "Static induction transistor published in 1984"

The insulated gate transistor: A new three-terminal MOS-controlled bipolar power device

Abstract: A new three-terminal power device, called the insulated gate transistor (IGT), with voltage-controlled output characteristics is described. In this device, the best features of the existing families of bipolar devices and power MOSFET's are combined to achieve optimal device characteristics for low-frequency power-control applications. Devices with 600-V blocking capability fabricated using a vertical DMOS process exhibit 20 times the conduction current density of an equivalent power MOSFET and five times that of an equivalent bipolar transistor operating at a current gain of 10. Typical gate turn-off times have been measured to range from 10 to 50 µs.

Series voltage regulator with limited current consumption at low input voltages

Abstract: A series voltage regulator having a regulating transistor (T 1 ) arranged with its emitter-to-collector path in a series arm of the regulator, the base of which is controlled via a control transistor (T 2 ) by a first differential amplifier (V) which compares a reference voltage (U REF ) with a voltage proportional to the voltage (U 2 ) of the regulator output. A differential circuit (V 2 ) which compares the collector-to-emitter voltage of the regulating transistor (T 1 ) with an auxiliary voltage (U 3 ) is provided, the output of which is followed by a current limiting circuit (T 3 ) which acts upon control transistor (T 2 ). The auxiliary voltage (U 3 ) is larger than the collector-to-emitter voltage of the regulating transistor (T 1 ) which occurs at the beginning of the saturation state of the regulating transistor. The current limiting circuit (T 3 ) limits the current delivered by the control transistor (T 2 ) to the base of the regulating transistor (T 1 ) as soon as the differential circuit (V 2 ) detects a drop in the collector-to-emitter voltage of the regulating transistor (T 1 ) to the auxiliary voltage (U 3 ). The auxiliary voltage (U 3 ) may be controlled proportionally to the regulator output current.

Noise associated with distributed resistance of MOSFET gate structures in integrated circuits

Abstract: The effect of thermal voltage fluctuations in a resistive gate matrix perpendicular to the direction of channel current, in a MOSFET, are treated in detail. A general formula is derived to arrive at channel current fluctuations for an arbitrary gate matrix layout. This formulation is an extension of the analysis done by Thornber and is valid for frequencies at which the distributed RC time constants associated with the gate matrix are not important. The results of this analysis can be used to design low-noise resistive gate structures.

Two-dimensional solid-state image sensor device

Abstract: A two-dimensional solid-state image sensor device, comprising: a plurality of picture cells which are two-dimensionally arranged in column and row directions, and each of which comprises a static induction transistor having drain and source regions with one conductivity type which are disposed on opposite sides of a high resistance semiconductor channel region, and control and shielding gate regions with the other conductivity type which are adjacent to the channel region to control a current flowing between the drain and source regions, and a transparent electrode disposed via a capacitance on at least a portion of the control gate region, in a manner that light is incident through the transparent electrode to the control gate region in which the charge produced by the light excitation is stored to control the current; a plurality of selection lines, each of which connects the control gate regions in each column in common via the capacitances; and a plurality of signal readout lines, each of which connects the drain or source regions in each row in common. Each picture cell is selected in the column and row directions so that a signal is read out therefrom. The shielding gate regions are electrically connected in common in the column or row direction and electrically isolated in the remaining direction so that voltages are independently applied to the pixels.

Semiconductor device with electrostatic discharge protection.

Abstract: An input protection circuit for an MOS device uses a thick-oxide transistor connected as a diode between a metal bonding pad and ground. The channel width of this transistor is chosen to be sufficient to withstand large, short-duration current spikes caused by electrostatic discharge. More important, the spacing between a metal-to-silicon contact to the drain of this transistor and the channel of the transistor (where heat is generated), is chosen to be much larger than usual so the metal of the contact will not be melted by heat propagating along the silicon surface during the current spike due to ESD. This spacing feature also applies to circuits for output pads, or circuits using diode protection devices.

Composite circuit of bipolar transistors and field effect transistors

Abstract: A novel composite circuit comprises a first bipolar transistor with a collector of a first conductivity type connected to a first potential, an emitter of the first conductivity type connected to an output, a second bipolar transistor with a collector of the first conductivity type connected to the output and an emitter of the first conductivity type connected to a second potential, a field effect transistor of a second conductivity type with a gate connected to an input, a source connected to a third potential and a drain connected to the base of the first bipolar transistor, a field effect transistor of the first conductivity type with a gate connected to the input, a drain connected to the base of the first bipolar transistor, and a source connected to the base of the second bipolar transistor, and a unidirectional element inserted between the output and the drain of the field effect transistor of the first conductivity type and having a direction of rectification opposite to that of the PN junction formed between the base and emitter of the first bipolar transistor.

Power supply for gas discharge devices

Abstract: A low current, high voltage power supply for gas discharge devices, such as neon tubes. The power supply has a free-running oscillator which generates a high frequency voltage signal which drives a light-weight, compact transformer. The oscillator has a power transistor drive, and a second transistor is used to remove the base drive of the power transistor to render it non-conductive. The second transistor also provides a path for rapid evacuation of the charge carriers stored in the base-emitter junction of the power transistor to rapidly render it non-conductive when the second transistor is energized. A safety bypass circuit is provided should a fault occur with the gas discharge device.

Recessed gate static induction transistor fabrication

Abstract: A gate-source structure and fabrication method for a static induction transistor having improved gain and frequency characteristics and having relatively simple fabrication requirements. The method and the device are embodied by gate regions diffused into the bottom of parallel recessed grooves located in a high resistivity epitaxial semiconductor layer, the surface of the semiconductor layer having a previously diffused source region located between the recessed grooves. The walls of the recessed grooves are covered with silicon dioxide.

Solid state image sensing device with photometry function

Abstract: A solid state image sensing device having an array of pixels each including a static induction transistor and a capacitance connected to a gate thereof, a signal readout line connected to sources of the static induction transistors, a first scanning circuit for reading image signals out of the pixels successively in a destructive manner, a second scanning circuit for reading photometry signals out of preselected pixels in a non-destructive manner, an integrating circuit for integrating the photometry signals, a comparison circuit for comparing an integrated value with a predetermined value to produce a detection signal when the integrated value becomes equal to the predetermined value and a control circuit for controlling the first and second scanning circuits in accordance with the detection signal. When the detection signal is produced, the second scanning circuit is stopped and at the same time the first scanning circuit is initiated to readout all the pixels in a destructive manner.

Voltage regulator for alternating current generator

Abstract: A voltage regulating system for an automotive vehicle having a switching transistor connected to a field winding of an alternating current generator and a regulator for comparing a battery voltage with a reference value and for driving the transistor into a conductive state when the battery voltage is lower than the reference value. A current limiting circuit is provided for limiting the field current when the switching transistor is going to be driven into the conductive state over a predetermined interval, so that a maximum charging current can be obtained and an unfavorable heating of the switching transistor can be avoided.

Logic and amplifier cells

Abstract: Disclosed is a high-speed circuit in which a basic cell includes a high-speed first transistor (Q1) and a high-speed second transistor (Q2). Both the first and second transistors have high gain-bandwidth products. The second transistor (Q2) is a unipolar (field-effect) device which is connected in a cascode configuration with the first transistor (Q1). The uni­ polar device functions to control the operating point of the first transistor over a range from "on" to "off" as a function of the unipolar device operating at a point over the range from "on" to "off". The unipolar device is controlled by an input voltage signal applied to its gate.

TTL to CMOS input buffer circuit for minimizing power consumption

Abstract: A buffer circuit comprising a current source transistor, a switching transistor and a current sink transistor coupled in series is provided. Control electrodes of the switching transistor and current sink transistor are directly connected and coupled to an input voltage. The buffer circuit has an accurate switchpoint voltage which is substantially process and temperature independent, and the circuit does not consume power for input voltages having low and high CMOS levels.

High voltage bootstrapping buffer circuit

Abstract: A logic circuit comprises a first MOS transistor of a first conductive type having a gate connected to an input/output line and a source connected to a first power source, a second MOS transistor of a second conductive type having a gate connected to the drain of the first MOS transistor, a source connected to a second power source, and a drain connected to the gate of the first MOS transistor, and a capacitor connected across the gate and source of the second MOS transistor. With the logic circuit of the invention it is possible to change a logic level without forming a direct path. This makes it possible to reduce load of a boosting circuit and a power supply. Also it can be used in a waveform shaping circuit.

Bi-MOS buffer circuit

Abstract: An improved buffer circuit is provided having an output stage for driving a load and a driver stage for driving said output stage. The output stage is constituted by a first MOS transistor to avoid problems found in bipolar output transistors which result from the amplitude of the output stage being influenced by the voltage Vbe of such output bipolar transistors. The driver stage, on the other hand, is formed of a bipolar transistor-MOS transistor composite logic cirucit. This driver stage includes an output circuit having a bipolar transistor for driving said first MOS transistor, and an input circuit including a second MOS transistor responsive to a predetermined input for rendering said bipolar transistor in the on or off state. The channel size of said first MOS transistor is larger than that of said second MOS transistor to give a device having an improved high operating speed.

A new approach to the modeling of nonuniformly doped short-channel MOSFET's

Abstract: A new doping transformation procedure for the modeling of arbitrarily doped enhancement-mode MOSFET's is presented. The procedure is based on conservation of charge and electrostatic energy in the depletion region along with the conservation of surface potential and depletion width. The transformation can be extended to short-channel MOSFET's using a charge sharing approximation. Experimental results obtained on n-well CMOS devices with effective channel lengths down to 1.5 µm are used to verify the validity of the models for threshold voltage, drain conductance, and drain current.

Memory array biasing circuit for high speed CMOS device

Abstract: A current limiting, process compensating circuit for CMOS memory arrays is provided. A dual transistor bias circuit is connected to each of a pair of columns of the array with a four transistor voltage reference circuit having its output connected to the gates of the active P-channel transistor of each bias circuit. A first P-channel transistor of the voltage reference circuit is sized to be less than the P-channel transistor of the bias circuit and the other three N-channel transistors are sized to be the same as the second transistor of the bias circuit and the two transistors of each memory cell in the array. As supply voltage to the array moves up or down making more or less current available, the combined circuit maintains nearly constant current on the first transistor of each bias circuit while compensating for process variation.

Gate protection for a MOSFET

Abstract: This invention relates to a protection device of a semiconductor device. The present invention can prevent the drop of a gate breakdown voltage due to miniaturization of a device without impeding the high speed performance of the circuit attached thereto. The invention improves the voltage that can be applied to the input terminal of the device by reducing the surface breakdown voltage of a surface breakdown type MOS transistor, which is a principal member of a protection device, and reducing the resistance after the breakdown. This can be accomplished, for example, by increasing the concentration of a region in which the MOS transistor is disposed, by reducing the depth of the region, and so forth.

Band gap voltage reference circuit

Abstract: A band gap voltage reference circuit includes first and second NPN transistors coupled as differential pair having ratioed emitters, to produce an offset voltage, and third and fourth emitter-coupled PNP transistors connected as a current mirror to function as load devices for the first and second transistors. The emitters of the third and fourth transistors are coupled to a current source and also to a fifth PNP emitter follower transistor which drives the base of a sixth emitter follower transistor connected to the collector of a seventh transistor, the emitter of which is connected to a series string including first and second resistors. The emitter of the seventh transistor is coupled to the base of the first transistor and the junction between the first and second resistors is coupled to the base of the second transistor. The emitter of the sixth transistor is coupled to series connected third and fourth resistors, the junction of which is coupled to the base of the seventh transistor. The ratio of the first and second resistors is adjusted to cause a band gap voltage produced on the base of the seventh transistor to have a very low temperature coefficient. The third and fourth resistors are ratioed to produce an output voltage at the emitter of the sixth transistor which is scaled up from the band gap voltage.

Method of fabricating junction field effect transistors

Abstract: Junction field effect transistor, specifically a static induction transistor, and method of fabricating. A low resistivity N-type surface layer is formed at the surface of a high resistivity N-type epitaxial layer which has been grown on a low resistivity N-type substrate of silicon. The surface of the surface layer is coated with silicon dioxide and portions of the silicon dioxide layer are removed to expose alternating gate surface areas and source surface areas. P-type conductivity material is diffused into the silicon from the gate surface areas to produce zones of graded concentration. The difference in concentration of N-type conductivity imparting material in the surface layer and in the remainder of the epitaxial layer causes the resulting P-type gate regions to extend laterally toward each other so as to produce narrow channel regions at a depth beyond the surface layer while limiting the lateral extensions of the P-type gate regions adjacent to the surface. The device exhibits both high voltage gain and low gate capacitance.

Low power CMOS fuse circuit

Abstract: A fuse circuit as used in self-repairing memory devices or the like employs a CMOS inverter and a feedback transistor to provide zero static or standby current. The fuse is in series with the feedback transistor across the supply, and the CMOS inverter has as its input the node between the fuse and feedback transistor. The inverter output controls the gate of the feedback transistor, which is N-channel or P-channel, depending upon whether the circuit is connected for high or low voltage output.

Device for driving a power field-effect switching transistor

Abstract: Two auxiliary transistors (Ts2, Ts3) are provided in a device for driving a power field-effect switching transistor (Ts1). A capacitor (C1) can be connected in parallel with the gate-source capacitance (CGS) of the power switching transistor (Ts1), via the first auxiliary transistor (Ts2). The second auxiliary transistor (Ts3) makes it possible to short-circuit the gate-source capacitance (CGS). The capacitor (C1) can be charged from an input voltage source (UE) via a voltage regulator (SR). A further auxiliary transistor (Ts4), which in turn drives the auxiliary transistors (Ts2, Ts3), can be activated by means of a pulse-controlled constant-current source (IQ). This device is suitable for operation of a constant-current transformer on a variable input voltage. Switching on and off delays of the power field-effect switching transistor can be kept very small (Fig. 1).

Dynamic type semiconductor memory device

Abstract: A dynamic type semiconductor memory device is disclosed, which comprises an n-type semiconductor layer (14), at least one memory cell having a capacitor (10) for storing charges of an amount corresponding to a logic value and a first transistor (12) having source and drain regions (18, 20) formed in the surface area of the p-type semiconductor layer and for transferring charges to and from the capacitor (10), a first drive circuit (WL) for applying a voltage to the gate of the first transistor (12) through a word line (WL), a second drive circuit for selectively applying a voltage of one of first and second levels (VS, VC) through a bit line (BL) and the first transistor (12) to the capacitor (10), and a bias circuit for applying a voltage to the substrate (10). The first transistor (12) of the memory device is a p-channel transistor formed in the n-type semiconductor layer (16) which is formed in the surface area of a p-type semiconductor layer (14). The bias circuit includes a charge pump section (41) for setting the potential of the substrate at a third level (VB) lower than the first voltage (VS).

Opposed gate-source transistor

Abstract: A field-effect transistor (FET) and a corresponding method for its fabrication, the transistor having a source and a gate located at opposite faces of an active channel region formed in a substrate, the source being substantially shorter in effective length than the gate and located symmetrically with respect to the gate. The transistor also has two drains, located one at each end of the channel region, and charge carriers flow from the source to the drains in two paths, under control of the same gate. Electrical contact with the source is made from beneath the substrate, while contact with the gate and drains is made from above. The resulting device has a large incremental transconductance and relatively small parasitic impedances, and therefore can operate at much higher frequencies than conventional FET's.

Brushless D.C. motor having two conductors per phase energized alternately by complementary-conductivity-type semiconductors controlled by the same rotor-position signal, at times modified by a compensating technique

Abstract: A one-phase motor has two conductors energized alternately via respective pnp and npn transistors and from the same output of a Hall-IC, without polarity inversion. When the Hall signal goes high the first transistor goes conductive and the second non-conductive, or vice versa. Capacitive delay elements slow down the switching-ON and -OFF of the two transistors. The capacitive delay elements have the undesired effect that, in response to the self-same change in the value of the Hall signal, the signal at the base of the OFF transistor changes comparatively quickly to switch the same ON, whereas the signal at the base of the ON transistor changes comparatively slowly to switch the latter off, which can lead to both being briefly conductive simultaneously, leading to voltage spikes and precluding safe dissipation of inductive energy in the transistors themselves. A coupling capacitor connects the transistors at their bases and has a capacitance value such that it develops and maintains a substantially fixed potential difference between the two bases. This causes the change in base potential at the ON-going transistor to be retarded in dependence upon the otherwise slower change occurring in the base potential of the OFF-going transistor, and furthermore causes the OFF-going transistor to become non-conductive before the ON-going transistor becomes conductive. This too helps to make it safe to dissipate in the OFF-going transistor the stored energy of the associated wound conductor.

Protection circuit for integrated circuits

Abstract: A protection circuit for an integrated circuit that is connected across a power source includes a first transistor and a zener diode or equivalent circuit arrangement for causing the first transistor to conduct if the integrated circuit receives an excessive voltage from the power source. A measuring resistor is connected to the emitter of the first transistor, and a voltage drop appears across the measuring resistor if the first transistor conducts. A comparator is provided to compare the voltage across the measuring resistor to a reference voltage. The output of the comparator drives the base of a second transistor, the emitter of which is connected to the collector of the first transistor and the collector of which is connected to the base of the first transistor. Current through the second transistor renders the first transistor more conductive.

Current limit technique for multiple-emitter vertical power transistor

Abstract: Circuitry (18, 20, 22, 24) for current limiting the output current of a power substrate PNP transistor (2...n) comprised of a plurality of emitters (e.g. 260). A resistor (8) is placed between a fraction of the plurality of emitters (e.g. 8) and a source of supply voltage. When the power device is turned on, the current is drawn through the resistor causing a voltage drop thereacross. This voltage drop is monitored and when it reaches a certain level, a control signal is generated which ultimately results in limiting the conducted current of the power transistor.

Charge-control analysis of class E tuned power amplifier with only one inductor and one capacitor in load network

Abstract: The following paper presents the charge-control analysis of operation of the transistor as a switch in the inverter circuit in which the collector current is constant while the transistor is saturated. This paper presents the charge-control analysis of the class E high-efficiency switching-mode tuned power amplifier with only 1 inductor and 1 capacitor in the load network, along with experimental results. In this amplifier, the collector current increases linearly with time while the transistor is saturated. We assume linear charge parameters of the transistor, and rectangular-wave base-drive current. The following are determined: the waveforms of all components of the base current and the base stored charge, the switching times, the driving power, and the power gain. A new definition of the overdrive factor of the transistor is introduced and the condition of the transistor saturation is discussed. It is shown that the base current necessary to drive the transistor to the edge of saturation increases with frequency f for f > f_{\beta} .

Programmable read-only memory (PROM) device having reduced programming voltage capability

Abstract: A programmable read-only memory device comprising a memory cell transistor which has a floating gate and a control gate formed above the floating gate. The programmable read-only memory device further comprises a means for delaying the application timing of a high voltage to the control gate from that of a high voltage to the drain of the memory cell transistor when a data programming operation is performed by applying the high voltage to the control gate and the drain of the memory cell transistor, thereby ensuring reliable a data write operation even at a low programming voltage.

TTL tristate device with reduced output capacitance

Abstract: An improved TTL tristate device with reduced output capacitance incorporates an active discharge sequence of three elements including first and second active transistor elements (Q8, Q7) in an inversion coupling and a third passive element comprising a passive diode cluster (D3, D4, D5) coupled between the base of the second transistor element (Q7) and the enable gate. The passive diode cluster is operatively arranged for delivering base drive current to the base of the second transistor (Q7) when the enable gate (A) is at high potential for operation of the output device in the bistate mode. The passive diode cluster also operatively diverts base drive current away from the base of the second transistor (Q7) when the enable gate (A) is at low potential for operation of the output device in the high impedance third state with reduced output capacitance. The first transistor element (Q8) of the active discharge sequence coupled to the base of the pull-down transistor element (Q4) follows in phase at its collector the potential maintained by the enable gate (A). It actively conducts, discharges and diverts capacitive feedback Miller current from the base of the pull-down transistor element (Q4) when the enable gate is at low potential, and presents a high impedance to current in the direction of the base of the pull-down transistor element (Q4) when the enable gate is at high potential. The power resistors to the active discharge sequence are arranged in a Y network with a capacitive center node.