Showing papers on "Static induction transistor published in 1986"

Static and dynamic analysis of amorphous-silicon field-effect transistors

Abstract: Analytical expressions have been developed for the analysis of static and dynamic behaviour of hydrogenated-amorphous-silicon based field-effect transistors. The current/voltage, capacitances and transcapacitances/voltage characteristics are related to the material parameters. The characteristic temperature, Tc, of the exponential band-tail states distribution is shown to influence strongly their shape and magnitude. An exact integration of the potential in the structure has allowed us to give expressions for the source and drain resistances. Finally, we present an equivalent circuit of a-Si:H TFT which can be employed in circuit simulation for the optimisation of integrated circuits.

Forming memory transistors with varying gate oxide thicknesses

Abstract: A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.

Study of the quasi-saturation effect in VDMOS transistors

Abstract: The quasi-saturation effect in VDMOS transistors is studied in detail. It is shown that such behavior is due to carrier velocity saturation in the JFET region of the device. Two-dimensional numerical simulation is carried out to study the quasi-saturation effect and its relation to different device design parameters. Experimental results over a wide range of voltage and current levels are used to verify calculated dc characteristics. In addition, the design constraint on p-body spacing in order to avoid the quasi-saturation effect is defined.

Observation of hot-hole injection in NMOS transistors using a modified floating-gate technique

Abstract: A modified floating-gate technique for measuring small gate currents in MOSFET's with very high resolution (0.01 fA) is described. Using this technique, gate oxide currents due to hot-carrier injection are measured in n-channel MOSFET's. The conventional negative channel hot-electron gate oxide current is observed near V_{g} = V_{d} and a small positive gate current occurs at low V g . We argue that the dependencies of this small positive current on V g and gate length, together with results from a separate floating-source experiment, are consistent only with hot-hole injection.

The role of the device surface in the high voltage behaviour of the GaAs MESFET

Abstract: Two dimensional computer simulation of the GaAs MESFET in the presence of a uniform surface charge predicted initial gate-drain avalanche voltages at variance with experiment in two respects: (a) The dependence of initial avalanche voltage upon gate length was weak compared with that evident in practice. (b) The absolute values of voltage were smaller by a factor of typically 3 than those observed experimentally. Examination of the potential and charge distributions revealed, even at low gate-drain potentials, electric fields near the drain end of the gate of sufficient magnitude to cause field emission. Electrons emitted in a direction parallel to the GaAs surface may occupy states in the forbidden band, which would result in a dynamic excess of charge residing on the surface immediately adjacent to the drain end of the gate. Inclusion of this effect in the computer model resulted in a simulated device behavior which is now similar to that found in practice.

BIMOS logic gate

Abstract: A BIMOS circuit is provided wherein an output terminal is coupled between upper and lower NPN push-pull transistors for providing high current drive capability along with no d.c. power dissipation. A first MOS transistor circuit is coupled to the lower transistor for biasing the lower transistor. A second MOS transistor circuit is coupled between an input terminal and both the upper transistor and the first MOS transistor circuit for providing a high impedance at the input and for biasing both the upper transistor and the first MOS transistor circuit, wherein the first circuit is biased with a larger voltage than the upper transistor for improving the switching speed of the output signal.

Field effect semiconductor device having improved voltage breakdown characteristics

Abstract: A semiconductor device including a field effect transistor of the D-MOS type which is composed of substructures and in which further surface zones are provided in the intermediate spaced between the regularly arranged substructures in order to improve the field distribution in the semiconductor body, as a result of which the breakdown voltage of the transistor is increased. The further surface zones can be provided without additional processing steps being required and need not be contacted at the main surface.

Comparison of drain structures in n-channel MOSFET's

Abstract: Practical limitations in channel lengths for n-channel MOSFET'S under 5-V operation are discussed for conventional arsenic-drain, phosphorus-drain, phosphorus-arsenic double diffused drain (DDD), and lightly doped drain (LDD) structures. Process parameter dependence of device characteristics and optimal process conditions are also evaluated for each drain structure. It is clarified that the minimum usable channel length is about 0.7-µm, which is realized by the DDD and LDD devices. In these devices, the hot-carrier-induced device degradation is no longer a major restriction on minimum channel length, but the short-channel effect and the parasitic bipolar breakdown are dominant restrictions. The phosphorus drain with a shallow junction formed by rapid thermal annealing can expand the arsenic drain limitation.

Voltage-switching device

Abstract: In a voltage-switching device for such applications as the control of electron tube grids in the field of radar or telecommunications, the total voltages to be switched are distributed at the terminals of a series-connected array of MOS field-effect transistors, thereby ensuring that each individual transistor is not liable to carry voltages in excess of such values which could result in transistor damage or destruction.

An analytical model for the power bipolar-MOS transistor

Abstract: This paper presents an analytical model for the I–V characteristics of the bipolar-MOS power transistor, also known as IGT or COMFET. Good agreement between this model and experiments is found over a wide range of carrier lifetime and current density. The predicted trade-off between the forward voltage drop and device turn-off time (0.4–10 μsec) has been verified by experiment. For even shorter switching time, the model predicts only a moderate increase in VF. Adding a more heavily doped buffer epitaxial layer is shown to only slightly increase VF but offers several important benefits. The comparison between n-channel and p-channel devices is discussed using the model and the forward voltage drops for the two types of devices are shown to differ by only a small percentage in spite of the large difference in electron and hole mobilities.

Experimental study on current gain of BSIT

Abstract: A means to improve the current gain h FS of the BSIT in a high drain current region has been derived from an experimental study about the dependency of the h FS versus drain current relationship on the channel width, the gate junction depth, and the impurity concentration in the n-high-resistivity drain region. The BSIT, designed in this manner and including 9000 channels in a chip of 7 × 10 mm2, exhibits a current gain over 100 and high switching speeds, a rise time of 200 ns, a storage time of 200 ns and a fall time of 25 ns at a drain current of 50 A.

SIT Image sensor: Design considerations and characteristics

Abstract: This paper concerns a new solid-state imaging device using a static induction transistor (SIT). The device has a single SIT/pixel structure previously proposed by Nishizawa et al. The authors developed a new serial readout area array configuration suitable for standard TV format, and its operational characteristics have been analyzed using a simplified model. Image sensors consisting of 170(H) × 124(V) pixels were fabricated using a combined SIT and MOS process, and their measured characteristics agree well with the analysis. Signal current as large as 94 µA was obtained at an exposure value of 0.17 lx . s without any output amplifier, and it is expected that sensitivity will be improved with a decrease in the charge storage capacitance of the SIT gate.

Transistor protection circuit for automotive motor control applications

Abstract: A protection circuit for the power transistor of an automotive motor control circuit The protection circuit comprises a protection transistor, a resistor, and a Zener diode The emitter-collector circuit of the protection transistor is connected in series with the resistor across the primary conduction path of the power transistor, with the resistor connected across the conduction control terminals of the power transistor The Zener diode is connected in series with the emitter-base circuit of the protection transistor across the motor, with the Zener diode poled to oppose current flow through the emitter-base circuit Transient inductive voltage generated across the motor upon removal of an externally applied control signal exceeds the reverse breakdown threshold of the Zener diode and biases the protection transistor conductive The protection transistor, in turn, directs current through the resistor to develop a bias voltage which biases the power transistor into a partially conductive state for slowly dissipating the inductive transient Source voltage transients due to load dump conditions are ineffective to bias the power transistor conductive

Method for lubricating a high capacity dram cell

Abstract: A dynamic random access memory cell (14) is disclosed which is characterized by a high capacity storage element and small lateral wafer area. The cell (14) is constructed with a word line (40) overlying a split bit line (48, 50), with an underlying transistor 30, and yet thereunder a high capacitance capacitor (34). The word line (40) includes a member (42) isolated from the bit line (36) and formed therethrough to provide the transistor gate conductor. The transistor gate insulator (44) covers the gate conductor (42), and is encircled by a transistor semiconductor region (46) forming a vertical transistor conduction channel. The split bit line elements (48, 50) are in electrical contact with an underlying transistor drain region (126). The transistor conduction channel (46) is also in contact with an underlying transistor source region forming one plate (52) of the capacitor (34). The capacitor plate (52) is a core which is enclosed annularly by dielectric isolation (54). Another semiconductor capacitor plate (56) encircles the dielectric isolation (54).

Multi-driver integrated circuit

Abstract: A monolithic integrated circuit (IC) chip in which is formed a multi-driver power circuit, with each driver circuit including one output power transistor, is partitioned such that the power transistor of each driver circuit, formed in the IC, is spaced apart from those of any other driver circuit a distance sufficiently large to ensure the generation of a temperature differential between the power transistors of the different driver circuits when their power dissipation is different. A thermal sensor is formed in close proximity to each output power transistor, and as far away as possible from the other power transistors of the IC, whereby each thermal sensor is thermally, tightly, coupled to its associated power transistor. Each thermal sensor is electrically coupled to the base of its associated power transistor for controlling the conductivity of its associated power transistor when the power dissipation of its associated power transistor and its resulting temperature exceeds a predetermined level.

Switching circuit utilizing a field effect transistor

Abstract: A switching circuit that utilizes an N-channel field effect transistor. The circuit can be used in a generator voltage regulator wherein the drain and source of the transistor are connected in series with the field winding of the generator. The circuit includes a capacitor that is repetitively charged and discharged. At the end of the charge period a gate bias voltage is developed that is applied to the gate of the transistor. The magnitude of the gate bias voltage that is developed is the sum of the capacitor voltage and the voltage of a voltage source. The capacitor is allowed to discharge until the gate bias voltage decreases to a value that is high enough to maintain the transistor conductive whereupon the discharge period is terminated and the capacitor is recharged. The system responds to the magnitude of the output voltage of the generator relative to a reference voltage and will cause the transistor to be biased conductive or nonconductive for total time periods that are equal to the sum of a plurality of consecutively occurring timing periods.

CMOS output circuit device

Abstract: A signal output circuit device according to the present invention comprises a first MOS transistor whose conduction is controlled by the potential given to its gate terminal, and gives the high level potential that is supplied by a high level voltage source to the output terminal, a diode which is inserted between the high level voltage source and the first MOS transistor so as to have its forward direction in the direction from the high level voltage source to the first MOS transistor, a second MOS transistor whose conduction is controlled by the potential given to its gate terminal, and supplies the low level potential supplied by a low level voltage source to the output terminal, and a diode which is inserted between the low level voltage source and the second MOS transistor so as to have its forward direction in the direction from the second MOS transistor to the low level voltage source.

Method and circuit for providing adjustable control of short circuit current through a semiconductor device

Abstract: Power Field Effect Transistors are commonly used to provide a series conduction path between a source of operating potential (12) and a load (14). A problem occurs if the load should cause the transistor to become a short circuit during which time rush currents across the FET (10) may seriously damage or even destroy the FET. A solution for limiting short circuit current flow in a Field Effect Transistor (10) and to limit the power dissipated therein includes sensing a rise in the drain-to-source voltage of the transistor and clamping the gate-to-source voltage to a predetermined adjustable value thereby reducing the magnitude of the short circuit current flow to within the safe operating characteristics of the device. A comparator switch circuit (32, 36) is responsive to the drain-to-source voltage of the FET exceeding a reference voltage value for clamping the gate-to-source voltage to a predetermined reduced voltage. A trimmable resistive network (40) is connected between the gate and the source electrode of the transistor for adjusting the gate-to-source clamped voltage potential to compensate for variations in transistor transductances from one transistor to the next that may be used in conjunction with the electronic circuitry.

Fast switching charge pump

Abstract: A charge pump implemented in a CMOS monolithic circuit provides a precise output charging current source or current sink with fast switching characteristics. Each of two CMOS output transistors is connected via a transmission gate to a transistor having a constant current flow through it. An MOS capacitor is connected to the gates of the constant current transistors. When a transmission gate is closed, the respective output transistor is coupled to the constant current transistor in a current mirror configuration. The output transistor is quickly switched on to cause a step change in output current.

MOS Pass transistor turn-off transient analysis

Abstract: Errors induced by turn-off transients are one fundamental limit in precision switched capacitor circuits. This paper presents detailed pass transistor turn-off transient analysis. Conventional single-lump models which assume quasi-static operation can introduce substantial errors for high-speed analog applications. New distributed and two-lump models have been constructed to analyze pass transistor turn-off transients in the diffusion mode of operation. A pass transistor test chip including a new selectively doped pass transistor approach has been designed, fabricated, and tested to verify the transient analysis. Measured performance of the nonuniformly doped pass transistors shows advantages in reducing transient charge errors.

Dimming circuit having switching transistor protection means

Abstract: A dimming circuit adjusts the light output of a lamp by controlling the current flow in the lamp that is connected to a transistor, through turning on and off the transistor with a predetermined timing which is changed by the control signal from a control signal generating circuit. The dimming circuit has a protective circuit for applying an off-state command signal to switch the transistor to the off-state by detecting an excess current flowing in the transistor when an input signal is applied as a control signal for switching the transistor to the on-state.

Transistor structure for high temperature logic circuits with insulation around source and drain regions

Abstract: A high temperature logic field effect transistor. By surrounding the source and drain pn junctions with electrically insulative material, except where a channel runs between the source and drain, a logic field effect transistor whose on/off current ratio can still have a high value at high temperatures. The transistor can be of any standard MOS technology, such as pMOS, nMOS, or CMOS.

Bidirectional output semiconductor field effect transistor and method for its maufacture

Abstract: A high voltage bidirectional output semiconductor field effect transistor (BOSFET) is disclosed which is turned on from the electrical output of a photovoltaic stack which is energized from an LED. The process for manufacture of the device is also disclosed. The BOSFET device consists of two lateral field effect transistors formed in an implanted N(-) region in a P(-) substrate. Two spaced drain regions feed inwardly toward a common N(+) source region separated from the drains by respective P type diffusions. The surface of these diffusions can be inverted by application of voltage to the suitably disposed gate electrode. The depletion field between channel and drain regions is well controlled over the surface of the device. The source contact remains close to the potential of the gate contact at all times so that the device can be used for high voltage switching of either polarity. A diode, PNP transistor and resistor are integrated into the same chip containing the lateral BOSFET device to form a solid state relay circuit having characteristics similar to a reed relay. The diode defines a forward conduction path from a photovoltaic pile voltage source directly to the BOSFET gate so that the BOSFET gate capacitance can be quickly charged during turn-on. The PNP transistor is a high gain transistor coupled to the diode and to the input resistance of the circuit. The input impedance of the circuit is reduced by the gain of the transistor when the photovoltaic output voltage is turned off and its voltage drops to below the gate voltage by about 0.6 volt to turn on the transistor. This allows the BOSFET to quickly turn off as though the circuit had a relatively low input impedance. Another control circuit is disclosed which employs a dV/dt suppression clamp circuit and a regenerative turn-off circuit.

Semiconductor memory device with high voltage switch

Abstract: A semiconductor memory device according to the present invention includes a first high-voltage switch (20) formed by a first transistor (21), a second transistor (22), a first capacitor (23) and a third transistor (24) and a second high-voltage switch (30) formed by a fourth transistor (31), a fifth transistor (32), a second capacitor (33) and a sixth transistor (34). In a write cycle, input data are stored in capacitors (25, 35). In an erase cycle, the second high-voltage switch (30) is driven by a clock signal (φ2) to make the control gate line (4) rise at a high voltage. In a program cycle, the first high-voltage switch (20) is driven by a clock signal (φ1) to make the bit line of the bit to be written with data "0" rise at a high voltge, and upon completion of the program cycle, charges stored in the capacitor (25) are discharged to reset a column latch. Thus, the device requires no inverter and may be provided with only one high voltage source.

Gate oxide integrity of NMOS transistor arrays

Abstract: The time-dependent dielectric breakdown (TDDB) of the channel oxide on n-channel MOS 1000-transistor arrays was investigated as a function of voltage stress on the gate and transistor temperature. The gate oxide is 25 nm thick. The field acceleration factor derived from the TDDB measurements is a linear function of the reciprocal temperature, in agreement with a thermodynamic model proposed by McPherson and Baglee. The thermal activation energy is a function of the temperature and consequently is not described by a simple Arrhenius equation. The field acceleration factor and effective temperature acceleration factor, as determined by the measurements, are used to project failure rates which are many orders of magnitude less than one failure in 109h for 10-V 55°C operation of the 1000- transistor array.

Multifunction floating fet circuit

Abstract: A transistor circuit is provided with a symmetrical floating configuration for attaining multi-­function operation of a transistor (20) having symmetrical source and drain characteristics, preferably a GaAs MESFET. The circuit includes a balun (30) which may be configured as a transformer, a differential amplifier, or a magic-tee waveguide depending on the frequency of signals to be processed by the circuit. Balanced terminals of the balun may be directly or capacitively coupled to source and drain terminals of the transistor (20). Tuning circuits (70, 72) are employed for applying signals having different frequencies to the transistor and for extracting intermodulation products generated by the transistor in response to the signals at the different frequencies. With the direct connection between the balun and the transistor, alternating voltages (via E, F, G) may be impressed between the terminals of the transistor to alternate source and drain regions of the transistor. Functions of amplification, modulation, bipolar attenuation, four-­quadrant multiplication and correlation, power frequency tripling, and mixing are obtainable. The transistor may be replaced with a pair of transistors connected in series or in antiparallel connection.

Proposed size-effect high-electron-mobility transistor

Abstract: We present a theoretical analysis of a high-electron-mobility transistor that uses the quantum size-effect to increase the energy gap of a thin InSb film that forms the channel of the device. The analysis is based on a considerable amount of available data. The device is predicted to have a cut-off frequency of the order of 439 GHz for a gate length of 0.5 μm. It is predicted to have a very high transconductance of 2.4 S per mm gate width, and a very high power handling capability of 1.4 A per mm gate width at a drain-to-source voltage of only 0.083 V, and it operates at 300 K.

Second breakdown prediction by two-dimensonal numerical analysis of BJT turnoff

Abstract: An isothermal two-dimensional numerical calculation of the potential and current distribution in an n+-p-n-n+bipolar power transistor driving an inductive load during its turnoff transient has been carried out. The transistor is initially considered to be in a heavily saturated ON-state and is then turned off by extracting a nearly constant base current. The simulation shows that during the turnoff transient, current constriction to the center of the emitter together with the increasing collector-emitter voltage produce a high electric field near the collector n-n+junction which can initiate avalanche injection. It has been found that the collector-current density is not uniform vertically (from collector to emitter) due to the current spreadout in the collector n-region. Previous one-dimensional analytical analyses of second breakdown did not consider this important effect. Thus, for an accurate prediction of reverse second breakdown voltage, the two-dimensional current flow should be considered.

Adaptive transistor drive circuit

Abstract: An adaptive transistor drive circuit including a multiple-emitter transistor, at least one emitter of which is connected to the drive circuit. When the drive current causes the transistor to saturate, the emitter connected to the drive circuit conducts a portion of the drive current to limit saturation of the transistor. A current source provides drive current which varies as a function of the current conducted by the collector of the transistor so as to maintain the transistor in saturation as the collector current and operating temperature vary.

Unbuffered TTL-to-ECL translator with temperature-compensated threshold voltage obtained from a constant-current reference voltage

Abstract: A circuit for translating TTL-to-ECL-type signals utilizes an unbuffered emitter-coupled transistor pair for shifting signal levels. The emitter-coupled transistor pair operates by switching a current from a current-source transistor, with the switching being performed against a temperature-compensated threshold voltage that is derived from a reference voltage provided to the current source transistor. Direct, unbuffered switching of the emitter-coupled transistor pair insures rapid, symmetrical response to the TTL signals that drive the transistor pair and produces high-quality, relatively undistorted ECL waveforms. Provision of a current-source reference voltage stabilized with respect to temperature also contributes to reduction of distortion in the ECL waveforms. The threshold voltage is obtained from the current source reference voltage through a current mirror circuit.