Showing papers on "Static induction transistor published in 1991"

Improved Analysis of Low Frequency Noise in Field‐Effect MOS Transistors

Abstract: An improved analysis of low frequency trapping noise in a MOS device is proposed. This analysis takes into account the supplementary fluctuations of the mobility induced by those of the interface charge. It enables an adequate description of the gate voltage dependence of the input equivalent gate voltage noise to be obtained in various actual situations. The outputs given by the Hooge mobility fluctuation model are also presented and discussed with respect to those obtained by the carrier number fluctuation model. In particular, the impact of the channel length or channel width, and the model type on the input gate voltage and drain current noise characteristics is studied and compared to typical experimental data. Finally, a procedure for the diagnosis of the low frequency noise sources in a MOS transistor is proposed.

Impact of surrounding gate transistor (SGT) for ultra-high-density LSI's

Abstract: A transistor with compact structures for future MOS devices is discussed. This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits. By using this transistor, the occupied area of the CMOS inverter can be shrunk to 50% of that using planar transistors. Other advantages, such as steep cutoff characteristics, very small substrate bias effects, and high reliability, are discussed. Its structure, which allows for the enlargement of gate-controllability to the channel and electric field relaxation at the drain edge, is described. The advantages of this SGT for large-scale integration (LSI) devices is discussed. >

Multi-pillar surrounding gate transistor (M-SGT) for compact and high-speed circuits

Abstract: The M-SGT has a three-dimensional structure, which consists of the source, gate, and drain arranged vertically. The gate electrode surrounds the crowded multipillar silicon islands. Because all the sidewalls of the pillars are used effectively as the transistor channel, the M-SGT has a high-shrinkage feature. The area occupied by the M-SGT can be shrunk to less than 30% of that occupied by the planar transistor. The small occupied area and the mesh-structured gate electrode lead to the small junction capacitance and the small gate electrode RC delay, resulting in high-speed operation. The fabrication of the M-SGT CMOS inverter chain is discussed. The propagation delay reduces to 40%, compared with the planar transistor inverter chain. >

Split-gate field effect transistor

Abstract: A field effect transistor having a gate voltage swing in the transistor channel varying as a function of position between the drain and the source. The gate voltage swing in the transistor channel may be made to vary as a function of position by making the threshold voltage a function of position. Alternatively, a split-gate device may be used by applying a voltage between the gates. In both cases, the electric field near the source is raised to accelerate the electrons thereby decreasing electron transit time.

Ferroelectric switching of a field‐effect transistor with a lithium niobate gate insulator

Abstract: A field‐effect transistor in which the ferroelectric lithium niobate (LiNbO3) replaces the oxide in a conventional metal‐oxide‐semiconductor transistor has been fabricated. The channel conductance of this device has been shown to be strongly affected by the application of voltage pulses between the gate of the device and the substrate. A reduction of channel current of nearly 140 μA was observed after the application of a voltage pulse of −30 V and partially restored with a+10‐V pulse. This behavior was found to be consistent with the influence of the polarization charge of the LiNbO3 layer on the carriers in the channel. This is the first observation of such behavior in a metal‐ferroelectric‐semiconductor field‐effect transistor without the growth of a buffer layer between the semiconductor and ferroelectric to prevent charge injection.

Silicon condenser microphone with integrated field-effect transistor

Abstract: A silicon condenser microphone is described, which works with an integrated field-effect transistor (FET). The gate of the transistor corresponds to the membrane of the microphone. Between the membrane and the gate oxide is a small air gap. The drain current of the transistor is controlled by the deflections of the membrane. The structure, which carries the FET and which is placed beyond the membrane, can have very small lateral dimensions. This results in small values of air-gap streaming losses and high air-gap compliances, thus yielding a good acoustic behaviour. The design of a silicon microphone with suspended-gate FET is described and experimental results of frequency response and noise are presented. The measured sensitivities are in the range 0.1–1 mV/Pa, which is about 15 dB lower than the calculated values. The reduction in sensitivity is caused by the silicon fabrication process of the microphones and can be eliminated. The frequency response is smooth up to 30 kHz. The noise measurement shows a 1/ f slope, which is typical for the noise behaviour of the FET.

Load current monitor for MOS driver

Abstract: An integrated circuit chip includes a MOS driver transistor and a relatively small MOS current-monitor transistor having their sources connected to a circuit ground point and their gates connected together to a control-voltage conductor. Current through the monitor transistor flows to a DC voltage supply conductor through a field effect transistor. A differential amplifier has one input connected to the drain of the driver transistor and the other input connected to the drain of the monitor transistor. The output of the differential amplifier is connected to the gate of the field effect transistor to force the drain voltage of the monitor transistor to be equal to the drain voltage of the driver transistor. The current flowing through the small monitor transistor has a constant proportionality with the load current even as the load current approaches zero. With the addition of a differential voltage amplifier having an output connected to the control-voltage conductor, having one input connected to a circuit ground point, and the other input connected to a control-current input pad, the current from the monitor transistor is fedback via a current mirror circuit to the other input of the voltage amplifier, so that the entire circuit can be made to perform as a current amplifier, e.g. driver-load-current/input-control current. By connecting one end of an external precision resistor to the control-current-input pad of the chip and applying a control voltage to the opposite end of the precision resistor, a control current proportional to the control voltage is caused to flow through the control-circuit-input pad. The combination performs as a current amplifier.

Vertical floating-gate transistor

Abstract: An electrically erasable, programmable, read-only-memory, floating-gate, metal-oxide-semiconductor transistor constructed in a trench extending through layers of P-type and N-type material formed on a semiconductor substrate. The floating-gate transistor is comprised of two source-drain regions, a channel region, a floating gate, a programming gate, and gate-oxide layers and is characterized by a floating-gate to channel capacitance that is small relative to the programming-gate to floating-gate capacitance, thereby allowing charging of the floating gate using programming and erasing voltages of less magnitude than might otherwise be necessary.

Effect of the electromagnetic environment on the single electron transistor

Abstract: The influence of envirommental impedances on tunneling rates in a single electron transistor circuit is investigated. Effects of the finite gate capacitance and of stray capacitances at the tunnel junctions are considered. For the case of a low impedance environment the electron tunneling rates reduce to the so-called global rule rate while for a high impedance environment a modification of the so-called local rule rate arises from the stray capacitances. Special emphasis is given to the dependence of the current on the gate voltage which determines the sensitivity of electrometers based on the transistor setup. It is found that a higher sensitivity of the electrometer can be achieved by means of asymmetric transistors.

Voltage regulator having bias current control circuit

Abstract: This invention relates to a bias current control circuit which drives a power MOS transistor. Since the power MOS transistor has a large capacitance which is formed between a gate and a channel, it is needed to provide a circuit which is able to sufficiently supply a drive current to the gate. Such a circuit increases a consumption current because the circuit has to always flow the current to drive the gate. This invention provides a circuit which cut the consumption current in the circuit when the transistor is not driven, and increases a consumption current in the circuit in order to keep a gate current when the transistor is driven.

A method of simultaneously fabricating an insulated gate-field-effect transistor and a bipolar transistor

Abstract: An insulated-gate field-effect transistor (426, 452) has reduced gate oxide stress. According to one embodiment, the control gate (458) has a doped region (460) adjacent the source end of the transistor (452), and an undoped dielectric portion (462) adjacent the gate end. According to another embodiment, the drain end of the conductive gate (434) is disposed on top of a thick insulator region (432) that also acts to mitigate the high electric fields present when the transistor is subjected to a high voltage transient.

Second-order predistortion circuit for use with laser diode

Abstract: A second-order predistortion circuit (12) for linearizing a nonlinear device (10) having a transfer function of the form F = C₁I₁ - C₂(I₁)², where I1 is a current applied to an input of the nonlinear device (10), and C1 and C2 are constants. The nonlinear device (10) is typically a laser diode. The predistortion circuit (12) includes a field effect transistor (20) biased for square law operation. An Input voltage (32) is applied between the gate (22) and source (24) electrodes of the field effect transistor (20). An amplifier (14) is connected between the drain electrode (26) of the field effect transistor (20) and the input of the nonlinear device (10). The gain of the amplifier (14) is selected to minimize second-order distortion in the output of the nonlinear device (10) as a function of the input voltage (32) to the field effect transistor (20).

Zero-voltage crossing detector for soft-switching devices

Abstract: A zero-voltage crossing detector includes a transistor circuit in combination with comparator circuitry for determining when the voltage across a soft-switching device crosses zero. The transistor circuit includes a series combination of a detector transistor and a source, or emitter, load resistance coupled across the soft-switching device. The gate, or base, of the transistor is coupled via a resistive voltage divider to a dc supply. The source, or emitter, of the transistor is coupled to the comparator circuitry for comparing the voltage across the load resistance to a zero-voltage reference. During intervals when the voltage across the soft-switching device is greater than the input voltage to the detector transistor, the detector transistor is off, causing the output of the transistor circuit to equal the input voltage. Othewise, the detector transistor is active and the output voltage equals the voltage across the soft-switching device, so that the comparator circuitry generates signals to indicate the zero-voltage crossings.

Semiconductor on insulator transistor

Abstract: The described embodiments of the present invention provide a method and structure for actively controlling the voltage applied to the channel of field effect transistors. In the described embodiments, a transistor connected to the channel region is fabricated. The channel transistor has opposite conductivity type to the transistor using the main channel region. The source of the channel transistor is connected to the channel and the drain of the channel transistor is connected to a reference voltage. The same gate is used to control the channel transistor and the main transistor. When a voltage which causes the main transistor to be on is applied, the channel transistor is off, thus allowing the channel to float and allowing higher drive current. On the other hand, when a voltage to turn off the main transistor is applied, the channel transistor is turned on, thus clamping the channel region to the reference voltage. This allows for consistent threshold voltage control of the main transistor. In a preferred embodiment, the channel of the main transistor is used as the source of the channel transistor and the gate of the main transistor extends onto the channel region of the channel transistor. The reference voltage is then connected to the drain region which is formed on the opposite side of the channel transistor channel region from the main transistor's channel.

Ring oscillator circuit having improved frequency stability with respect to temperature, supply voltage, and semiconductor process variations

Abstract: A compensation circuit (14) for a ring oscillator (12) having an odd plurality of series-connected CMOS inverter stages includes first and second P-channel transistors and a resistor. The first transistor (32) has a source coupled to VDD and a gate coupled to ground. The resistor (34) is coupled between the drain of the first transistor and ground. The second transistor (36) has a source coupled to VDD, a gate coupled to the drain of the first transistor, and a drain coupled to a supply node of each of the inverter stages of the ring oscillator for providing a supply voltage that is compensated with respect to voltage, temperature, and semiconductor processing variables. In operation, the conductivity of the first transistor inversely controls the conductivity of the second transistor that supplies a compensated power to the inverter stages. The compensated power controls the conductivity of the transistors in the ring oscillator and the corresponding frequency of oscillation.

Biasing circuit for sense amplifier

Abstract: When a common source line of sense amplifiers in a semiconductor memory device is pulled down via a pull-down transistor, a current level signal indicative of the level of the current which flows through the pull-down transistor is generated. The current level signal is compared with a reference level signal indicative of an allowable maximum level of the current which flows through the pull-down transistor. When the current level signal exceeds the allowable maximum level, the pull-down transistor is controlled to reduce the current flowing therethrough.

Static RAM memory cell using N-channel MOS transistors

Abstract: A floating gate NMOS enhancement mode transistor is utilized in an NMOS SRAM thereby reducing power consumption, size, and circuit complexity of the memory cell. The gate of the load transistor is allowed to float with no galvanic connection to the memory cell circuit. A bias voltage is induced on the gate of the load transistor by capacitances of the gate with the source, the drain, and the bulk semiconductor, and the conductance is maintained below conduction threshold. Gate bias is established by tailoring of the gate capacitances and by the removal of charge using UV light as necessary.

N-channel pull-up transistor with reduced body effect

Abstract: A CMOS output buffer circuit employing an N-channel pull-up transistor with reduced body effect includes an N-channel pull-up transistor (N2), an N-channel coupling transistor (N1), and an N-channel discharging transistor (N3). The pull-up transistor has its drain connected to an upper power supply potential (VCC), its source connected to an output node (20), its gate connected to a first internal node (B), and its local substrate connected to a second internal node (A). The coupling transistor has its source connected to the second internal node (A), its drain connected to the source of the pull-up transistor, its gate connected to the first internal node (B), and its local substrate connected to the local substrate of the pull-up transitor (N2). The discharging transistor has its drain connected to the second internal node (A), its source connected to a lower power supply potential (VCC), its gate connected to a third internal node (C), and its local substrate connected to the lower power supply potential (VSS). The coupling transistor and the discharging transistor serve to reduce the body effect on the pull-up transistor (N2) and to provide higher immunity from noise on the upper power supply potential (VCC).

Word line driver circuit for dynamic random access memories

Abstract: A wordline driver circuit for reading the contents of a Dynamic Random Access Memory (DRAM). The circuit is implemented in CMOS and is capable of pulling the wordlines to a negative potential with respect to the substrate, thereby decreasing the access time. An NMOS pull-down transistor channel is implemented as a P-well within an N-well. Applying a negative potential to the source of the pull-down transistor permits the transistor to be switched so that a negative potential is applied to the wordline when the NMOS pull-down transistor is gated into conduction. A PMOS pull-up transistor is serially connected to the NMOS pull-down transistor drain, permitting the wordline to be driven positively.

Temperature compensated circuit for controlling load current

Abstract: A temperature compensated control circuit includes a load transistor which passes the load current and has an on-resistance which varies with temperature. To provide temperature compensation, first and second pilot transistors are integrated with the load transistor such that as the load transistor heats-up due to the load current passing through the on-resistance of the load transistor, the first and second pilot transistors heat-up due to heat conduction from the load transistor. Each of the pilot transistors has an on-resistance which varies proportionally or similarly to the on-resistance of the load transistor. A first current source supplies a first level of current to the on-resistance of the first pilot transistor to develop a first reference voltage, and a second current source supplies a second level of current to the on-resistance of the second pilot transistor to develop a second reference voltage. The range between the first and second reference voltages corresponds to an acceptable range of load current. A voltage corresponding to the load current is sensed across the load transistor, and the control circuit controls the load current to maintain the sensed voltage within the range.

High speed threshold crossing detector with reset

Abstract: The present invention provides a high speed, all CMOS comparator utilizing positive feedback and DC voltage clamping. The circuit comprises two source-coupled PMOS transistors with their sources coupled to a current source or a supply voltage. A third PMOS transistor is coupled between the source of the first PMOS transistor and a terminal of a current mirror. The gate of this third PMOS transistor is coupled to the output node in such a way as to provide positive feedback to the circuit. As the negative input voltage becomes lower than the positive input voltage, the current passing through the second PMOS transistor increases and the current passing through the first PMOS transistor decreases. As the output node increases in voltage, the equivalent resistance of the third PMOS transistor increases, thus decreasing the current through the first PMOS transistor. This acts to increase the current being provided to the output node and increases the drive characteristics of the circuit. As a further improvement to the circuit, a voltage-clamping device is included in the design.

Circuitry and method for discharging a drain of a cell of a non-volatile semiconductor memory

Abstract: Circuitry for discharging a drain of a cell of a non-volatile semiconductor memory is described. A discharge transistor is coupled between (1) the drain of the cell and (2) ground for selectably (a) providing a discharge paths to ground for the drain of the cell when the discharge transistor is enabled and (b) not providing a discharge path to ground for the drain of the cell when the discharge transistor is not enabled. Circuitry is coupled to the discharge transistor for enabling the discharge transistor for a duration that both begins and ends (1) after a first operation is performed with respect to the cell and (2) before a verify operation is performed with respect to the cell.

Method of forming a thin film field effect transistor having a drain channel junction that is spaced from the gate electrode

Abstract: A process for forming a thin film field effect transistor, particularly adapted for use in SDRAM devices using CMOS flip-flop circuits, wherein the transistor has a drain-channel P-N junction that is precisely spaced from the gate electrode, the process involving the etch back of the edge of the gate electrode, either prior to ion implantation to form the source and drain, or following the implantation.

Protection apparatus for series pass MOSFETS

Abstract: In order to restrict the voltage across the gate oxide of an input pass-through transistor which operates as an input signal source to a MOS inverter, a MOS transistor wired as a MOS diode is connected between the source and gate electrode of the pass-through transistor. The diode connected transistor allows the use of a thin oxide device for the pass-through transistor which enables a high transconductance device to be employed while restricting the voltage across the gate oxide of the pass-through transistor to an acceptable value.

Substrate bias voltage detection circuit

Abstract: A substrate bias detection circuit is disclosed The circuit includes first and second transistors, where the first transistor has its source coupled to the substrate and where the second transistor has its source coupled to a common potential (ie, ground) The gate and drain of the first transistor are connected together, and to the gate of the second transistor Load devices are connected between the drains of the first and second transistors and a bias potential from a power supply node The threshold voltages of the first and second transistors may be different, with the difference determining the voltage that the substrate must reach, relative to the common potential, to cause the circuit to respond Upon the substrate reaching a voltage sufficient to turn the second transistor on, the drain of the second transistor will be pulled toward the common potential, indicating loss of substrate bias The circuit may be included into an integrated circuit in such a manner that power supply voltages may be disconnected from other circuitry in the event of loss of substrate bias, precluding the possibility of latchup in such other circuitry

Method of fabricating a high-performance insulated-gate-field-effect transistor and transistor fabricated by it

Abstract: An improved device fabrication method and transistor structure 36 provide shallow, heavily doped, source/drain junction regions 64 and a uniformly doped lower gate region 50 having a high concentration of dopants efficiently distributed near the gate electrode/gate interface 51. The gate, source, and drain terminals of transistor 36 may be interconnected to other neighboring or remote devices through the use of reacted refractory metal interconnect segments 98 and 100. Transistor structure 36 of the present invention may be constructed in an elevated source/drain format to include elevated source/drain junction regions 87 which may be fabricated simultaneous with a primary upper gate electrode region 88. This elevated source/drain junction feature is provided without added device processing complexity.

Circuit for measuring current in a power MOS transistor

Abstract: A circuit for measuring current in a power MOS transistor (M0) comprises second (M1) and third (M2) transistors in series of the same type and same technology as, but having a smaller surface than, the power transistor and arranged in parallel on the latter. The two series transistors have their gates connected to the gate of the power transistor. The current in transistor (M2) which is connected to the reference electrode of the power transistor is measured.

High power buffer with increased current stability

Abstract: A circuit buffers output in an integrated circuit. The circuit includes a circuit input, a circuit output, a power signal, a ground signal, a first transistor, a second transistor, a third transistor, a fourth transistor, variable resistance means, and control means. The variable resistance means is connected between the source of the first transistor and the drain of the second transistor. The variable resistance provides one of a first impedance and a second impedance between the source of the first transistor and drain of the second transistor in response to a control signal. The control means is connected to the control input means of the variable resistance means. After a voltage level transition on the circuit input and during a resulting voltage level transition on the circuit output, in response to the control means, the variable resistance means first provides the first impedance and then provides the second impedance between the source of the first transistor and drain of the second transistor.

Semiconductor nonvolatile memory device for controlling the potentials on bit lines

Abstract: A nonvolatile semiconductor memory device comprising a power source terminal and a P-channel MOS transistor. A low power-source voltage is applied to the terminal during a read period. The source of the P-channel MOS transistor is coupled to the power source terminal. The conduction of the MOS transistor is controlled by data-writing operation. The drain of the MOS transistor is connected by a node to a plurality of bit lines. The device further comprises a plurality of memory cells and a plurality of N-channel MOS transistor. The memory cells have double-gate structure, each having a source coupled to the ground and a drain coupled to the corresponding bit line. Each N-channel MOS transistor has a source and a drain connected to the ground and the corresponding bit line, respectively, for discharging the bit line. Each N-channel MOS transistor is rendered conductive temporarily when the supply of the high power source voltage to the power source terminal is started, whereby the potential of the corresponding bit line is decreased. The bit-line potential is decreased sufficiently since the P-channel MOS transistors have a conductance greater than that of any other transistor incorporated in the device.

Control circuit for a force commutated power transistor

Abstract: The present invention relates to a control circuit for a power transistor (1) including a circuit (3) for driving the gate (10) of the said transistor controlled by a control signal (4). The control circuit according to the invention is especially notable in that the said drive circuit (3) is also controlled by two negative-feedback signals, namely a signal proportional to the gradient of the voltage across the terminals of the transistor and a signal proportional to the gradient of the main current of the transistor. Application to MOS type field-effect transistors (MOSFET).