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Showing papers on "Static induction transistor published in 1992"


Journal ArticleDOI
TL;DR: A functional MOS transistor is proposed which works more intelligently than a mere switching device, and is ideal for ULSI implementation.
Abstract: A functional MOS transistor is proposed which works more intelligently than a mere switching device. The functional transistor calculates the weighted sum of all input signals at the gate level, and controls the 'on' and 'off' of the transistor based on the result of such a weighted sum operation. Since the function is quite analogous to that of biological neurons, the device is named a neuron MOSFET, or neuMOS (vMOS). The device is composed of a floating gate and multiples of input gates that capacitively interact with the floating gate. As the gate-level sum operation is performed in a voltage mode utilizing the capacitive coupling effect, essentially no power dissipation occurs in the calculation, making the device ideal for ULSI implementation. The basic characteristics of neuron MOSFETs as well as of simple circuit blocks are analyzed based on a simple transistor model and experiments. Making use of its very powerful function, a number of interesting circuit applications are explored. A soft hardware logic circuit implemented by neuMOS transistors is also proposed. >

689 citations


Patent
04 Jun 1992
TL;DR: In this paper, a driver circuit for driving top and bottom power transistors stacked between two supply terminals is provided, which includes shoot-through reduction means for monitoring the gate-to-source voltages of the two transistors so as to inhibit the turning-on of each power transistor until the gate to source voltage of the other power transistor has fallen to a voltage level indicative of one being OFF.
Abstract: A driver circuit for driving top and bottom power transistors stacked between two supply terminals is provided. The driver circuit includes shoot-through reduction means for monitoring the gate-to-source voltages of the two power transistors so as to inhibit the turning-ON of each power transistor until the gate-to-source voltage of the other power transistor has fallen to a voltage level indicative of the other transistor being OFF. Additionally, the driver circuit which can utilize a bootstrap capacitor for providing enhanced voltages to drive the top power transistor, also includes a bootstrap capacitor recharge means to monitor the output voltage of the circuit so as to inhibit the turning-ON of the top power transistor until the bootstrap capacitor has had sufficient time to recharge.

197 citations


Patent
26 Oct 1992
TL;DR: In this paper, a semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate, and a first vertical transistor stack (122) was formed.
Abstract: A semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate (12). A first vertical transistor stack (122) is formed. A second vertical transistor stack (124) is formed. The first vertical transistor stack (122) has a transistor (100) underlying a transistor (104). The second vertical transistor stack (124) has a transistor (102) underlying a transistor (106). The transistors (100 and 104) are connected in series, and the transistors (102 and 106) are connected in series. In a preferred form, transistors (100 and 102) are electrically connected as latch transistors for a semiconductor memory device and transistors (106 and 104) are connected as pass transistors. Two vertical stacks (126 and 128) form electrical interconnections (118 and 120) and resistive devices (134 and 138) for the semiconductor memory device.

146 citations


Journal ArticleDOI
TL;DR: In this article, the authors used charge-pumping measurements and device simulations to analyze the electron injection and to determine its exact position in the transistor channel, and determined the width of the spacer between both transistor gate has been determined to be an important injection parameter.
Abstract: When applying a high voltage to the floating gate of a split-gate transistor, enhanced hot-electron injection is observed that can be used for 5-V compatible EPROM or flash EEPROM device operation. The current collected on the gate is equal to the total electron injection current. Charge-pumping measurements and device simulations are used to analyze the electron injection and to determine its exact position in the transistor channel. Gate currents only show a weak dependence on both transistor channel lengths. The width of the spacer between both transistor gate has, however, been determined to be an important injection parameter. >

86 citations


Patent
19 Jun 1992
TL;DR: In this article, a circuit for providing reference voltages to be used by sense amplifiers of output circuitry of an integrated circuit memory array to allow the sense amplifier to ascertain the values stored by memory cells of the array is described.
Abstract: A circuit for providing reference voltages to be used by sense amplifiers of output circuitry of an integrated circuit memory array to allow the sense amplifiers to ascertain the values stored by memory cells of the array The circuit includes a first branch which has transistor circuitry for establishing a reference current, a second branch of the circuit including a first transistor device and apparatus for mirroring the reference current through the first transistor device, and a plurality of output branches each connected to a sense amplifier to provide a reference voltage to be used by the sense amplifier Each of the output branches includes a second transistor device with characteristics essentially identical to the characteristics of the first transistor device Apparatus is included in the output branches for providing voltages at all terminals of the second transistor devices equal to the voltages at all terminals of the first transistor device so that the reference current through each of the second transistor devices is forced to be identical to that through the first transistor device The second branch is replicated to increase current available and circuit speed

85 citations


Patent
03 Feb 1992
TL;DR: In this article, a performance enhancing conductor (27) is employed to reduce a transistor's (10) on resistance and to also reduce the transistor's parasitic gate to drain capacitance.
Abstract: A performance enhancing conductor (27) is employed to reduce a transistor's (10) on resistance and to also reduce the transistor's (10) parasitic gate to drain capacitance (32). The performance enhancing conductor (27) covers the transistor's (10) gate (22) and a portion of the drain region (18, 19) that is adjacent the transistor's channel (20). The performance enhancing conductor (27) is isolated from the gate (22) by an insulator (24, 26).

76 citations


Patent
23 Jul 1992
TL;DR: In this paper, a trench is constructed between each adjacent pair of field rings and is insulated either by oxide formed on the sidewalls thereof or by an oxide filling, allowing the field rings to be very closely spaced together.
Abstract: For a vertical DMOS power transistor or a high voltage bipolar transistor, an edge termination at the perimeter of the die surrounding the active transistor cells includes multiple spaced apart field rings. A trench is located between each adjacent pair of field rings and is insulated either by oxide formed on the sidewalls thereof or by an oxide filling. The insulated trenches allow the field rings to be very closely spaced together. Advantageously the trenches may be formed in the same process steps as are the trenched gate electrodes of the active portion of the transistor. This structure eliminates the necessity for fabricating thick field oxide underlying a conventional field plate termination, and hence allows fabrication of a transistor without the need for a field plate termination, and in which the multiple field rings are suitable for a transistor device having a breakdown voltage in the range of 20 to 150 volts. The trenches advantageously eliminate the process sensitivity of using multi field ring terminations with low resistivity semiconductor material.

51 citations


Journal ArticleDOI
TL;DR: In this article, a twin-MOSFET structure is proposed for suppression of the kink and parasitic bipolar effects in SOI MOS transistors, which is also an attractive candidate to provide satisfactory linear device operation at liquid He temperature.
Abstract: A twin-MOSFET structure is proposed for suppression of the kink and parasitic bipolar effects in SOI MOS transistors. It is also an attractive candidate to provide satisfactory linear device operation at liquid He temperature. The device consists of two transistors in series with a common gate but it operates as a single transistor. Kink effect can be confined to the one “slave” transistor while the other “master” transistor can be kept free from the kink effect. If the gate length of the master transistor is larger than that of the slave one, the kink-free master transistor dominates the overall output characteristics of the device. As a consequence, the kink effect is suppressed in the overall output characteristics of the device. Furthermore, the parasitic bipolar effect in SOI MOSFETs is also significantly reduced and the saturation drain output impedance as well as the output breakdown characteristics are drastically improved. Kink-free and very flat output characteristics are obtained at both room and liquid He (4.2 K) temperatures.

51 citations


Patent
26 Aug 1992
TL;DR: In this paper, a circuit for driving a power transistor device has been proposed, where an amplifier is coupled to a current sensing device for providing a substantially linear control signal proportional to the current in the power transistor devices, and a detector is provided for detecting when the current level in the device greater than a threshold level is detected.
Abstract: A circuit and method for driving a power transistor device. The circuit for driving a power transistor device has a driver having an input and an output, the output coupled to a control input of the power transistor device and the input coupled to a primary control voltage source for driving the power transistor device. A current sensing device is coupled to the power transistor device for providing a signal proportional to the current in the power transistor device. An amplifier is coupled to the current sensing device for providing a substantially linear control signal proportional to the current in the power transistor device, the linear control signal being provided to the input of the driver as a secondary drive signal for driving the power transistor device when a current level in the power transistor device greater than a threshold level is detected. A detector is provided for detecting when the current in the power transistor device is greater than the threshold level. The detector is coupled to the current sensing device and to a reference level source, and provides an overcurrent signal to the driver for switching the driver from being driven by the primary control voltage source to the secondary drive signal. The secondary drive signal drives the driver so as to reduce the current level in the power transistor device. The driven power transistor device is preferably a power MOSFET or IGBT.

48 citations


Patent
Kiyohiro Furutani1
31 Dec 1992
TL;DR: In this paper, a reference voltage generating circuit with an improved temperature compensation function is presented, where the temperature compensation is achieved by appropriately setting a drain current of each transistor, and the transistors for temperature compensation can be formed in the same manufacturing steps.
Abstract: In a reference voltage generating circuit having an improved temperature compensation function, a PMOS transistor forming a constant voltage circuit has the same characteristics as a PMOS transistor forming a negative feedback circuit. As an ambient temperature changes, gate-source voltage and drain current characteristics of each transistor are shifted, but temperature compensation is achieved by appropriately setting a drain current of each transistor. Transistors for the temperature compensation can be formed in the same manufacturing steps, so that temperature compensating effect can be obtained without an additional manufacturing step.

48 citations


Patent
Roger R. Lee1
21 Aug 1992
TL;DR: A programmable read-only memory device and method of fabrication with an antifuse in the drain node of a field effect transistor was described in this article, where the antifuses were placed at the drain and gate to avoid source reverse bias.
Abstract: A programmable read-only memory device and method of fabrication are disclosed having an antifuse in the drain node of a field effect transistor. Programming is accomplished by imposing a high voltage on the transistor drain and gate which causes the antifuse to be a closed circuit; otherwise, the transistor appears as an open circuit. Locating the antifuse in the drain node as opposed to the source node avoids problems of source reverse bias.

Patent
17 Dec 1992
TL;DR: An MOS transistor output circuit is provided in this article which limits or unlimits the amplitude of the output potential for reducing undesired radiation, malfunctions due to noises and heat generated and for high-speed operation of logic circuits.
Abstract: A transistor (2P) permitted to select whether to operate as a common-source circuit or as a source follower type circuit is connected in series with a transistor (1P) operating as a common-source circuit. This selection is achieved by the control of a switching circuit (SP). Selection is permitted to be made whether to oscillate the amplitude of an output potential over the full range or to limit the amplitude by the amount of a threshold level of the transistor. An MOS transistor output circuit is provided which limits or unlimits the amplitude of the output potential for reducing undesired radiation, malfunctions due to noises and heat generated and for high-speed operation of logic circuits. (FIG. 1)

Patent
02 Mar 1992
TL;DR: In this paper, a mesh-shaped p-type buried layers 6 are formed on an n-type layer 3 by base diffusion and a gate electrode can be led out, which can be used as a base.
Abstract: PURPOSE:To obtain a means, with which a bipolar static induction transistor (SIT) having high-speed and large-current characteristics can coexist as part of an IC, by a method wherein p-type buried layers are arranged in a mesh shape in contact to an n buried layer in one semiconductor insular region isolated. CONSTITUTION:In the structure formed in an insular region II, mesh-shaped p-type buried layers 6 are formed on an n buried layer 3. Therefore, one of the layers 6 is connected with a p-type layer 12 to be formed by base diffusion and a gate electrode can be led out. By applying bias between the layer 12 and an n-type epitaxial layer, a depletion layer extends to the periphery of the p-type layer, the switching ON and the switching OFF of current between a source (n layer 16) and a drain (n layer 14) are operated and a vertical type SIT having high-speed and large-current switch characteristics can be obtained by a process for microscopical formation. The mesh- shaped p-type buried layer which is used as the gate electrode can be formed simultaneously with p-type buried layers for isolation and the p-type layer for leading out the gate electrode can be diffused simultaneously with the p-type layer which is used as a base. Thereby, an IC, in which the SIT and an n-p-n transistor coexist, can be obtained without increasing specially the manhour.

Patent
08 May 1992
TL;DR: In this paper, the authors present an asymmetric channel structure of the peripheral transistor, where the gap between the source contact and the gate electrode is set shorter than the distance between the drain contact and gate electrode, and a gate contact is electrically connected between a gate electrode and a metal gate line.
Abstract: A semiconductor integrated circuit device has a peripheral transistor having a strengthened ESD resistance for external connection. The peripheral transistor has a channel structure effective to release an electrostatic stress current more efficiently than an internal transistor of the semiconductor integrated circuit. In one embodiment, the peripheral transistor has a channel portion that is shorter than the channel portion of an internal transistor. In another embodiment, the peripheral transistor has a substrate contact, a ground line, and an additional resistor interconnection between them to efficiently release an electrostatic stress current. In another embodiment, the peripheral transistor has an asymmetric channel structure so that the distance between the source contact and the gate electrode is set shorter than the distance between the drain contact and the gate electrode. In another embodiment, the peripheral transistor has a drain region and a gate insulating film having a portion of the insulating film that is thinner than the rest of the gate insulating film. In another embodiment, a gate contact is electrically connected between a gate electrode and a metal gate line of the peripheral transistor to reduce a resistance therebetween. In another embodiment, the peripheral transistor has a transistor breakdown voltage that is smaller than a gate breakdown voltage to efficiently release electrostatic stress current.

Patent
07 Jan 1992
TL;DR: A circuit protection arrangement that is intended to be series connected in a line of the circuit comprises a transistor switch (1) that controls the line current and a control transistor (4) that controlled the base or gate voltage of the switching transistor and is responsive to an overcurrent through the switch.
Abstract: A circuit protection arrangement that is intended to be series connected in a line of the circuit comprises a transistor switch (1) that controls the line current and a control transistor (4) that controls the base or gate voltage of the switching transistor and is responsive to an overcurrent through the switching transistor. The arrangement includes a voltage source, for example a battery (3), a dc-dc converter (58/59) or a Seebeck device (43), applied to the base or gate of the switching transistor which biases the switching transistor into or toward conduction in normal operation. The arrangement enables the initial voltage drop that is required to turn the switching transistor (1) on to be reduced or eliminated while requiring relatively little current from the voltage source. The arrangement can be reset remotely by briefly removing the voltage source or load from the circuit.

Patent
28 Jul 1992
TL;DR: In this article, a laterally recessed channel region (LRC) of a vertical field effect transistor (VFE transistor) with drain regions having graded diffusion junctions (31) and two load transistors (112 and 115) was shown to be a vertical p-channel thin-film field effect transistors.
Abstract: The disclosure includes a vertical field-effect transistor (115) with a laterally recessed channel region (92), a vertical field-effect transistor (116) having a graded diffusion junction (31), a static random access memory cell (110) having a vertical n-channel field-effect transistor (116) and a vertical p-channel field-effect transistor (115) and methods of forming them. In one embodiment, a six-transistor static random access memory cell (110) has two pass transistors (111 and 114), which are planar n-channel field-effect transistors, two latch transistors (113 and 116), which are vertical n-channel field-effect transistors with drain regions having graded diffusion junctions (31), and two load transistors (112 and 115), which are vertical p-channel thin-film field-effect transistors having laterally recessed channel regions (92).

Patent
03 Sep 1992
TL;DR: In this paper, a reference voltage generator which compensates for temperature and VCC variations includes a constant current source and a MOS P-channel transistor, which is in saturation.
Abstract: A reference voltage generator which compensates for temperature and V CC variations includes a constant current source and a MOS P-channel transistor. The constant current source provides a constant current over a wide range of V CC that corresponds to biasing a p-channel transistor in a region where its resistance is constant. The output of the current source is supplied to the P-channel transistor, which is in saturation. The constant current provides a constant voltage drop across the P-channel transistor. Hence, a stable reference voltage is generated. Temperature compensation is provided by biasing the P-channel transistor to saturation and supplying a constant current that the corresponds to biasing a p-channel transistor where the resistance is substantially constant over a temperature range. The current causes a voltage drop across the P-channel transistor to maintain a stable reference voltage. Also, temperature compensation is further provided by utilizing the negative temperature coefficients of the resistors included in the constant current source.

Patent
01 Jul 1992
TL;DR: In this paper, a bipolar transistor Q 1 having a collector formed of a substrate region SUB of a MOS transistor M 1 and an emitter formed on the base and connected to a bit line BL is used for data readout.
Abstract: A bipolar transistor Q 1 having a collector formed of a substrate region SUB of a MOS transistor M 1 , a base formed of the drain region of the MOS transistor and an emitter formed on the base and connected to a bit line BL is connected between the bit line BL and a memory cell MC formed of the MOS transistor M 1 and and a capacitor C 1 and the current amplifying operation of a bipolar transistor is used for data readout.

Patent
11 Sep 1992
TL;DR: In this paper, a circuit utilizable for protecting an integrated circuit feature from electrostatic discharge is disclosed, where a first bipolar transistor has its emitter connected to the IC feature and its collector connected to ground.
Abstract: A circuit utilizable for protecting an integrated circuit feature from electrostatic discharge is disclosed. A first bipolar transistor has its emitter connected to the IC feature and its collector connected to ground. A second bipolar transistor has its emitter connected to the IC feature and its collector connected to its base and to the base of the first bipolar transistor. A field effect transistor has its gate and drain connected to the IC feature and its body connected to its source and to the collector and base of the second bipolar transistor and to the base of the first bipolar transistor. A diode has its cathode connected to the body and the source of the field effect transistor and to the collector and base of the second bipolar transistor and to the base of the first bipolar transistor.

Journal ArticleDOI
TL;DR: In this paper, the Scharfetter-Gummel expressions for both electron and hole current densities were derived and the current boundary conditions at the base contact were used in the calculations.
Abstract: Coupling the heat transfer equation with Poisson's and continuity equations in 1-D and taking into account carrier degeneracy, semiconductor band and temperature spatial distributions, the current-voltage characteristics of an n - p - n AlGaAs/GaAs heterojunction bipolar transistor are simulated. The Scharfetter-Gummel expressions for both electron and hole current densities are derived. Both voltage and current boundary conditions at the base contact are used in the calculations. The current modulation nature of bipolar transistor devices is revealed by using the current boundary condition. It is found that the temperature rise due to high current operation causes two effects: the current gain continuously declines after the base push-out is complete; and the negative differential resistance phenomenon occurs in the transistor current-voltage saturation region.

Patent
21 Jan 1992
TL;DR: In this paper, a polysilicon diode (24) is connected across a base-emitter junction of the bipolar transistor (10) and a poly-silicon resistor (38) in series with an emitter of a bipolar transistor.
Abstract: A protective circuit for an input to a bipolar transistor (10) capable of operating in the microwave frequency range. In a first embodiment, a polysilicon diode (24) is connected across a base-emitter junction of the bipolar transistor (10). In a second embodiment, a polysilicon resistor (38) is connected in series with an emitter of the bipolar transistor (10), and the polysilicon diode (24) is connected across the series combination of the base-emitter junction and the polysilicon resistor (38). The layout of the transistor (10) and the islands of polysilicon (23, 25) housing the diode is critical since the bipolar transistor (10) is capable of operating in the microwave frequency range. In a first layout, an island of polysilicon (25) is centered between two transistor regions (47 and 48). In an exterior diode layout, a transistor region (51) is centered between two islands of polysilicon (23 and 25).

Patent
08 Sep 1992
TL;DR: In this article, a DC/DC voltage converting device is obtained for boosting a DC power supply voltage to provide a higher output voltage, comprising soft start circuit 20 for gradually increasing the turning-on duration of transistor 34 in boosting circuit 30; pulse width control circuit 60 for providing a modulated pulse signal P2 to control the boosted voltage.
Abstract: A DC/DC voltage converting device is obtained for boosting a DC power supply voltage to provide a higher output voltage, comprising soft start circuit 20 for gradually increasing the turning-on duration of transistor 34 in boosting circuit 30; pulse width control circuit 60 for providing a modulated pulse signal P2 to control the boosted voltage. The device further comprises boosting circuit 30 including an inductor 32, diode 36 and transistor 34. Boosting circuit 30 provides a predetermined boosted voltage higher than the power supply voltage by alternately turning on and off transistor 34. The turning-on duration of transistor 34 is gradually increased during the initial operation period by soft start circuit 20, and is controlled by modulated pulse signal P2 during a stable operation period. The device further comprises gate circuit 40 having diode 46 and transistor 44, and step up circuit 70. Step up circuit 70 turns off transistor 44 during the initial operation period, and turns it on while transistor 34 is off during the stable operation period to allow an efficient current flow from boosting circuit 30 to output terminal 58. Any counter current flow from output terminal 58 to boosting circuit 30 is inhibited during the initial operation period.

Patent
Miyata Yutaka1, Mamoru Furuta1, Tatsuo Yoshioka1, Hiroshi Tsutsu1, Kawamura Tetsuya1 
09 Jan 1992
TL;DR: In this paper, an active matrix substrate includes a transparent substrate, pairs each having an n-type thin-film transistor and a p-type transistor formed on the transparent substrate.
Abstract: An active matrix substrate includes a transparent substrate, pairs each having an n-type thin-film transistor and a p-type thin-film transistor formed on the transparent substrate, gate bus lines and source bus lines connected to the n-type and p-type transistors for controlling the n-type and p-type transistors, and pixel-corresponding electrodes controlled by the transistor pairs respectively. Drains of an n-type transistor and a p-type transistor in each of the pairs are connected to each other via a related pixel corresponding electrode. First pulses are applied to gates of the n-type transistors. Second pulses are applied to gates of the p-type transistors. There is provided a difference in phase between the first pulses and the second pulses.

Patent
15 Jun 1992
TL;DR: In this paper, a data output buffer includes a data driving circuit having a pull-up transistor responsive to a first signal and a pulldown transistor responsiveness to a second signal, a first control circuit for regulating the slope of the first signal to be less steep after reaching the threshold of the pullup transistor, and a second control circuit that regulates the slope on the second signal.
Abstract: A data output buffer includes a data driving circuit having a pull-up transistor responsive to a first signal and a pull-down transistor responsive to a second signal, a first control circuit for regulating the slope of the first signal to be less steep after reaching the threshold of the pull-up transistor than before reaching the threshold of the pull-up transistor, and a second control circuit for regulating the slope of the second signal to be less steep after reaching the threshold of the pull-down transistor than before reaching the threshold of the pull-down transistor. As a result, noise generated by the transition of the output signal of the data output buffer is reduced without affecting operation speed.

Patent
09 Apr 1992
TL;DR: In this article, a photoelectric conversion element is provided under a channel region of each of the feedback gate transistor and the vertical selection transistor, whereby the sensitivity of the solid state image sensing device is increased and the smear thereof can be lowered.
Abstract: A solid state image sensing device is formed of a plurality of photo-sensing sections arranged in a two-dimensional fashion at a pixel unit in the horizontal and vertical directions. In this case, each of the plurality of photo-sensing sections is formed of a feedback gate transistor whose gate electrode and source electrode are both connected to a vertical signal line, a vertical selection transistor which is connected in series to the feedback gate transistor and whose gate electrode is connected to a horizontal selection line, and a photoelectric conversion element provided under a channel region of each of the feedback gate transistor and the vertical selection transistor, whereby the sensitivity of the solid state image sensing device is increased and the smear thereof can be lowered.

Patent
Yoshinori Okajima1
30 Jul 1992
TL;DR: In this article, the drain of the first P-channel MOS transistor is connected to the gate of the second p-channel mOS transistor, which has a threshold voltage (a gate potential with respect to a source potential) greater than that of the original P-Channel MOS transistors.
Abstract: A semiconductor integrated circuit includes a first P-channel MOS transistor and a second P-channel MOS transistor. The drain of the first P-channel MOS transistor is connected to the gate of the second P-channel MOS transistor. The second P-channel MOS transistor has a threshold voltage (a gate potential with respect to a source potential) greater than that of the first P-channel MOS transistor.

Journal ArticleDOI
TL;DR: The vortex flow transistor as discussed by the authors is a multiloop superconducting device that offers the prospect of a true three terminal device with good power gain, high speed and low operating power.
Abstract: The vortex flow transistor is a multiloop superconducting device that offers the prospect of a true three terminal device with good power gain, high speed and low operating power. The first such device has been fabricated using a controlled junction technology in high temperature superconductor. >

Patent
11 Sep 1992
TL;DR: In this paper, an ECL circuit for translating from CMOS to ECL levels is presented, which consists of a pair of emitter-coupled transistors and first MOS transistor coupled in series with a first base of the pair at one end of the source/drain current path of the first mOS transistor.
Abstract: An ECL circuit with power control is disclosed. The ECL circuit comprises a pair of emitter-coupled transistors with a current source transistor having its collector coupled to the coupled-emitters of the pair. Coupled in series with the base of the current source transistor is a first MOS transistor with its gate receiving an enable signal to control the first MOS transistor. As such, an activated first MOS transistor switches on the ECL circuit, and a de-activated first MOS transistor switches off the ECL circuit with no current through the current source transistor to provide a true power down of the ECL circuit. An ECL circuit for translating from CMOS to ECL levels is also disclosed. The ECL circuit comprises a pair of emitter-coupled transistors and first MOS transistor coupled in series with a first base of the pair at one end of the source/drain current path of the first MOS transistor. Another end of the source/drain current path of the first MOS transistor is coupled to a current-source voltage, while its gate receives an enable signal. Coupled in series with a second base of the pair at one end of the source/drain current path of the second MOS transistor is a second MOS transistor. Another end of the source/drain current path of the second MOS transistor is also coupled to the current-source voltage, while its gate receives an inverted enable signal. Thus, the pair has its two emitter-coupled transistors alternately switched on by the enable and inverted enable signals. An ECL circuit for multiplexing ECL inputs with CMOS select signals is further disclosed. The ECL circuit comprises the top portion of a conventional ECL multiplexer connected to a pair of Vcs current sources. The current sources are alternately selected by the N-channel MOS transistor coupled between the Vcs current source and one base of the n-p-n transistors.

Patent
01 Jul 1992
TL;DR: In this article, a tri-state output buffer circuit employs N-channel pull-up and pull-down transistors, with a P-channel and an Nchannel transistor responsive to the logic input.
Abstract: A tri-state output buffer circuit employs N-channel pull-up and pull-down transistors, with another N-channel transistor connected between the pull-up and pull-down transistors and having its gate connected to the low-voltage supply. An output node at one side of the pull-up transistor may be driven to a voltage higher than the supply, without subjecting the pull-up to hot-carrier effects or other deleterious effects of over-voltage. When in the high-impedance output state, the gate of the pull-up is shorted to an intermediate node which is the drain of the pull-down transistor, using a P-channel and an N-channel transistor responsive to the logic input. The voltage on the gate of the pull-up transistor is allowed to track the output up to the reduced voltage supply minus V TN when in the high-impedance state, by tying the gate of the pull-up transistor to the intermediate node; this prevents damage to the pull-up due to hot-carrier effects.

Patent
21 May 1992
TL;DR: In this paper, a driving circuit is provided for a power transistor connected to an inductive load, where a detection resistor is placed between ground and the emitter of the power transistor, and the driving circuit has a first portion which is capable of generating a first current which is a nonlinear function of the voltage across the detection resistance.
Abstract: A driving circuit is provided for a power transistor connected to an inductive load. A detection resistor is placed between ground and the emitter of the power transistor. The driving circuit has a first portion which is capable of generating a first current which is a non-linear function of the voltage across the detection resistance. A second portion of the driving circuit is used to generate a base current for the power transistor that is proportional to the first current. The non-linear function of the first current compensates for the non-linear gain with respect to collector current of the power transistor.