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Showing papers on "Static induction transistor published in 1993"


Patent
29 Nov 1993
TL;DR: In this article, a vertical field effect transistor (1400) and diode (1450) were formed on a single III-V substrate and the diode cathode and the transistor drain or collector were formed in a common layer (1408).
Abstract: A vertical field effect transistor (1400) and diode (1450) formed on a single III-V substrate. The diode cathode and the transistor drain or collector may be formed in a common layer (1408).

120 citations


Patent
18 Oct 1993
TL;DR: In this paper, the authors proposed a nonvolatile random access memory (NVRAM) cell that employs an enhancement mode nMOS transistor made as an accumulation mode transistor, which is preferred to use a non-reentrant (edgeless) gate transistor structure to further reduce edge effects.
Abstract: A non-volatile random access memory (NVRAM) cell that utilizes a simple, single-transistor DRAM cell configuration. The present NVRAM employs an enhancement mode nMOS transistor made as an accumulation mode transistor. The transistor has an n-type silicon carbide channel layer on a p-type silicon carbide buffer layer, with the channel and buffer layers being on a highly resistive silicon carbide substrate. The transistor also has n+ source and drain contact regions on the channel layer. A polysilicon/oxide/metal capacitor is preferably used which has a very low leakage current. Furthermore, this type of capacitor can be stacked on top of the transistor to save area and achieve high cell density. It is preferred to use a non-reentrant (edgeless) gate transistor structure to further reduce edge effects.

112 citations


Journal ArticleDOI
J.C. Huang1, G. Jackson1, S. Shanfield1, A. Platzker1, P. Saledas1, C. Weichert1 
TL;DR: In this paper, a model based on surface states was proposed to explain this phenomenon, which then led to the use of charge-screen layers and a double-recessed gate process to suppress surface effects.
Abstract: The authors determined that RF drain current degradation is responsible for the poor power performance of wide-recessed pseudomorphic high-electron-mobility transistors (PHEMTs). A model based on surface states was proposed to explain this phenomenon, which then led to the use of charge-screen layers and a double-recessed gate process to suppress surface effects. Combined, these two modifications increased the device's gate-drain reverse breakdown voltage without causing a degradation in the transistor's RF drain current. This allowed the simultaneous achievement of high power-added efficiency and high power density which established a new performance record for power PHEMTs at X- and Ku-bands. Delay time analysis of single- and double-recessed PHEMTs revealed that the benefit of a larger breakdown voltage in the latter device design came at the cost of a larger drain delay time. Drain delay accounted for 45% of the total delay when the 0.35- mu m double-recessed PHEMT was biased at V/sub ds/=6 V. >

88 citations


Patent
11 Feb 1993
TL;DR: The breakdown voltage of a VDMOS transistor is increased without depressing other electrical characteristics of the device by tying the potential of a field-isolation diffusion, formed under the edge portion of a strip of field oxide separating a matrix of source cells from a drain diffusion, to the source potential of the transistor as mentioned in this paper.
Abstract: The breakdown voltage of a VDMOS transistor is markedly increased without depressing other electrical characteristics of the device by tying the potential of a field-isolation diffusion, formed under the edge portion of a strip of field oxide separating a matrix of source cells from a drain diffusion, to the source potential of the transistor. This may be achieved by extending a body region of a peripheral source cell every given number of peripheral cells facing the strip of field-isolation structure until it intersects said field-isolation diffusion. By so connecting one peripheral source cell every given number of cells, the actual decrement of the overall channel width of the integrated transistor is negligible, thus leaving unaltered the electrical characteristics of the power transistor.

77 citations


Patent
15 Mar 1993
TL;DR: In this article, a gate electrode is removed for self-alignment to selectively implant impurities only into end portions of a source region and a drain region, and the impurity concentration in the channel region is ununiform.
Abstract: Insulating films formed on side walls of a gate electrode are removed for a self-alignment to selectively implant impurities only into end portions of a source region and a drain region. Therefore, p + -type semiconductor regions are selectively formed only on sides near a channel region of the source and the drain regions. A punch through of the source or drain region is prevented by the p + -type semiconductor regions controlling an inversion threshold voltage. Therefore, the impurity concentration of the p-type substrate can be settled low, and the semiconductor transistor device can be miniaturized without increasing a parasitic junction capacitance. Moreover, since the impurity concentration in the channel region is ununiform, a drivability of the transistor can be increased. As a result, a semiconductor transistor device with a high withstand voltage and a high drivability in which the inversion threshold voltage can be easily controlled, and a method for producing the same are provided.

68 citations


Patent
26 Nov 1993
TL;DR: A current limit circuit for protection of an intelligent power switch includes a series circuit of a sense transistor and a sense resistor coupled to the power semiconductor transistor switch so that the sense resistor current is a fraction of, and is proportional to, the power transistor current.
Abstract: A current limit circuit for protection of an intelligent power switch includes a series circuit of a sense transistor and a sense resistor coupled to the power semiconductor transistor switch so that the sense resistor current is a fraction of, and is proportional to, the power transistor current. A pull-down transistor is coupled to the control electrode of the power transistor switch. A feedback circuit including a series connection of a diode-connected transistor and a reference V source is coupled between the sense resistor and the control electrode of the pull down transistor. The feedback circuit produces a voltage level shift and the circuit provides an accurate limit on the power transistor current independent of any variations in threshold voltage.

57 citations


Patent
Mohamad M. Mojaradi1, Tuan A. Vo1
21 Dec 1993
TL;DR: A high current, high voltage transistor which can be easily electrically stacked to extend the voltage range and uses less silicon area than a conventional stacked transistor configuration and a configuration of field plates that provide the greatest breakdown voltages with the highest ohmic values as discussed by the authors.
Abstract: A high current, high voltage transistor which can be easily electrically stacked to extend the voltage range and uses less silicon area than a conventional stacked transistor configuration and a configuration of field plates that provide the greatest breakdown voltages with the highest ohmic values. Also, a star shaped field plate design which provides the greatest breakdown voltages with the highest ohmic values. The field plate is constructed using several concentric rings connected by fingers that are wider at towards the center of the concentric rings and narrower towards the perimeter of the concentric rings.

57 citations


Patent
Steven L. Merchant1, Emil Arnold1
08 Feb 1993
TL;DR: In this paper, a method and thin film transistor having a linear doping profile between the gate and drain regions was presented, which achieved a significantly high breakdown voltage of the order of 700 to 900 volts, much greater than that achieved in the prior art.
Abstract: The present invention is directed to a method and thin film transistor having a linear doping profile between the gate and drain regions. This is constructed in a particular manner in order to achieve a thin film transistor having a significantly high breakdown voltage of the order of 700 to 900 volts, much greater than that achieved in the prior art.

52 citations


Patent
Kazuhisa Kagawa1
02 Feb 1993
TL;DR: In this paper, an improved high-frequency high-power transistor includes a transistor chip and capacitors forming an RF shunting internal matching circuit, and the capacitors are connected with RF shoving wires to a collector pad to which the transistor chip is die-bonded.
Abstract: An improved high-frequency high-power transistor includes a transistor chip and capacitors forming an RF shunting internal matching circuit. The capacitors are connected with RF shunting wires to a collector pad to which the transistor chip is die-bonded. The wires have the same lengths and are disposed symmetrically relative to input and output leads of transistor cells within said transistor chip so that they uniformly influence the transistor cells.

49 citations


Patent
Bernard L. Morris1
28 Oct 1993
TL;DR: In this paper, an integrated circuit is disclosed comprising a first field effect transistor having a source connected to a first node and a gate connected to the second node, and a second field-effect transistor for protecting the first transistor from voltages that are greater than a predetermined nominal voltage.
Abstract: An integrated circuit is disclosed comprising a first field effect transistor having a source connected to a first node and a gate connected to a second node, and a second field effect transistor for protecting the first transistor from voltages applied to the first node and greater than a predetermined nominal voltage. The second transistor includes a drain connected to the second node, a source connected to the first node, and a gate connected to a third node. A constant voltage source is coupled to the third node and supplies a gate voltage to the gate of the second transistor such that a drain-source path of the second transistor does not conduct while voltage applied to the first node is generally less than the gate voltage plus a threshold voltage of the second transistor. The constant voltage source comprises a third field effect transistor having a drain and a gate connected to the third node, and a source coupled to a first power supply voltage, such that the gate voltage is substantially equal to the first power supply voltage minus a threshold voltage of the third transistor.

48 citations


Journal ArticleDOI
TL;DR: In this paper, a semi-physical transistor model is presented which is proven to be well suited for simulating analog h.f. ICs up to fT even in the high current region.
Abstract: In advanced silicon bipolar technologies very narrow emitter stripes can be realized. As a consequence, the transistors in high-frequency (h.f.) ICs should be operated at high current densities in order to obtain maximum operating speed. Therefore, in this paper a semi-physical compact transistor model is presented which is proven to be well suited for simulating analog h.f. ICs up to fT even in the high-current region. It is based on an improved version of the transistor model HICUM which has first been described in[1,2] and which was successfully applied for designing high-speed digital circuits. The model presented here, however, is not only superior in very-high-frequency applications but also in modeling narrow-emitter transistors. These advantages are obtained by accurately taking into account non-quasi-static transistor behavior, h.f. emitter current crowding, and emitter-periphery effects, as well as by improving the operating point dependence of basic parameters. Due to the physical nature of the model, the elements of the equivalent circuit can easily be calculated for arbitrary transistor geometries at arbitrary operating points and temperatures from a single set of specific electrical and technological data. This makes the model very well suited for circuit optimization. The compact model, which has been implemented in SPICE, was successfully verified by means of two-dimensional device simulations based on the doping profile of a real self-aligned double-polysilicon transistor. In order to be sure that verifying the compact model by device simulations replaces the measurements correctly, the model parameters were determined by device simulation too, but applying the methods used for experimental parameter extraction.

Patent
16 Apr 1993
TL;DR: In this article, the authors proposed a laterally spreading N-type diffusion region with impurity concentration level higher than P-type and N-Type wells but lower than source and drain regions.
Abstract: A CMIS transistor suitable for device miniaturization, elimination of degradation of operational characteristics by hot carrier effect, and elimination of decrease of threshold voltage caused by short channel effect, includes a laterally spreading N-type diffusion region having an impurity concentration level higher than P-type and N-type wells but lower than source and drain regions, such that the N-type diffusion region extends laterally into a part located immediately below an edge of an insulating gate and has a depth smaller than a depth of the source and drain regions. The device is thereby capable of increasing the width of depletion layer at the bottom of the source and drain regions while maintaining effectiveness as a punch-through stopper. Thereby, the junction capacitance at the source and drain regions is reduced and the operational speed of the device improved in the P-channel transistor part in the device. In the N-channel transistor part, an effective suppression of punch-through is achieved because of the small diffusion depth of the N-type diffusion region. Thereby, the decrease of threshold voltage caused by the short channel effect is effectively eliminated even when the gate length of the transistor is reduced.

Patent
10 Sep 1993
TL;DR: An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and the drain terminals of all other stages, is described in this paper.
Abstract: An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and drain terminals of all other stages, a second N type field effect control transistor device having drain and source terminals connecting the drain terminal and the gate terminal of the first switching transistor device, and a storage capacitor joined to the source terminal of the first device; a source of voltage to be pumped is connected to the drain terminal of the first device of the first stage. A first series of clock pulses is applied to the gate terminals of the first switching transistor devices in every other stage of the charge pump and to the gate terminals of the second control transistor devices in stages between; and a second series of clock pulses which do not overlap the first series of clock pulses is applied to the gate terminals of the first switching transistor devices in alternate stages of the charge pump and to the gate terminals of the second control transistor devices in stages between the alternate stages. These pulses cause the switching transistor to switch on and off in alternate stages in a manner that the gate terminal goes higher than the drain terminal so that charge is transferred without threshold drop between stages and high current as well as high voltage is pumped to the output terminal.

Patent
15 Apr 1993
TL;DR: In this article, a voltage-controlled current source (S1) is responsive to the input signal and applies a compensating current ΔIload which is equal and opposite to the load current variation caused by a change (ΔVin) in the input voltage to the emitter of the main transistor (Q3) to compensate for load current modulation ΔVbe.
Abstract: A compensating transistor (Q5) is connected in series with the collector of a main transistor (Q3), and a level shifted replica (Vin + V1) of an input signal (Vin) is applied to the base of the compensating transistor (Q5) to maintain a constant voltage difference between the base and collector of the main transistor (Q3) and compensate for base width modulation ΔVce. A voltage-controlled current source (S1) is responsive to the input signal (Vin) and applies a compensating current ΔIload which is equal and opposite to the load current variation caused by a change (ΔVin) in the input voltage (Vin) to the emitter of the main transistor (Q3) to compensate for load current modulation ΔVbe. Alternatively, the compensating current can be applied to the junction of the base of the main transistor (Q3) and the emitter of pre-distortion transistor (Q4) which has a base connected to receive the input signal (Vin). Another compensating transistor (Q12) applies a current (ΔIb) which is equal and opposite to a non-linear base current variation to the emitter or collector of the main transistor (Q3) to compensate for current gain modulation ΔIb. The modulation compensation arrangements are applicable to common-collector, common-base and common emitter amplifiers in single-ended and differential configurations, and to substantially all bipolar and field-effect transistor technologies.

Patent
28 May 1993
TL;DR: In this article, a circuit is provided for supplying a negative high voltage to an integrated circuit from a high positive voltage source Vpp, where the negative voltage is applied to a plurality of FLASH EPROM cells.
Abstract: A circuit is provided for supplying a negative high voltage to an integrated circuit from a high positive voltage source Vpp. The negative voltage is applied to a plurality of FLASH electrically erasable programmable read only memory (EPROM) cells. The circuit includes an oscillator coupled to a voltage converter which provides a periodic signal. The periodic signal is coupled to a charge pump (3) including three P-channel type transistors to produced the negative voltage. The source and drain of the first transistor (41) is coupled to the periodic signal. The second transistor's (43) gate and drain is coupled to a reference ground potential with the source coupled to the first transistor's gate. Finally, the third transistor's drain and gate is coupled to the first transistor's gate and the third transistor's source outputs negative voltage to floating gates of the plurality of FLASH EPROM cells during an erase operation. Further, the negative voltage generated is relatively precise, so no regulation is required.

Patent
02 Aug 1993
TL;DR: In this article, a non-volatile memory device with a multi-level gate structure has been presented, and the gate structures of the two regions are formed through a single etching process, so that the decreased processing number of photolithography simplifies overall process, and reduces the damage on the field oxide layer to enhance an insulating performance.
Abstract: The present invention discloses a non-volatile memory device having a multi-level gate structure. The storage cell transistor in the cell array region and the transistor in the peripheral circuit region have the same multi-level gate structure. Also, multi-level polycrystalline silicon layers in the peripheral circuit region are connected to each other, and thus utilized as an electrically singular gate electrode. The gate structures of the two regions are formed through a single etching process, so that the decreased processing number of photolithography simplifies overall process, and reduces the damage on the field oxide layer to thereby enhance an insulating performance.

Patent
04 Jan 1993
TL;DR: In this paper, the flyback voltage is felt through the vertical pnp transistor at the drain, which onducts to the substrate, which represents a power loss and a source of heat.
Abstract: When a field effect transistor is used to control the current through an inductive load, the flyback voltage is felt through the vertical pnp transistor at the drain, which onducts to the substrate. This current represents a power loss and a source of heat. This invention supplies a second lateral transistor which conducts this current back to the power supply.

Patent
Takanori Ozawa1
19 Mar 1993
TL;DR: In this article, a nonvolatile memory device with a field effect transistor for storing is described, which includes source and drain regions in a semiconductor substrate with a channel region interposed between them and a gate electrode above the channel region with a ferroelectric gate film sandwiched between them.
Abstract: A nonvolatile memory device having a field effect transistor for storing, which includes source and drain regions in a semiconductor substrate with a channel region interposed between them and a gate electrode above the channel region with a ferroelectric gate film sandwiched between them. Barrier metal is formed in contact with the source region of the field effect transistor for storing to make a Schottky diode in serial connection with the field effect transistor for storing. In reading information, voltage is applied to a serial circuit consisting of the field effect transistor for storing and the Schottky diode to turn the Schottky diode on.

Patent
07 Oct 1993
TL;DR: In this article, an emitter follower is constructed of a first transistor with a first resistor connected between the emitter electrode of the first transistor and an output terminal, with input signal applied to the base of the second transistor.
Abstract: An impedance converter includes an emitter follower constructed of a first transistor with a first resistor connected between an emitter electrode of the first transistor and an output terminal. Input to the emitter follower is provided by a second transistor of complementary type, with input signal applied to the base of the second transistor and the emitter electrode of the second transistor coupled to the base of the first transistor with a second resistor. Bias current in the second transistor and second resistor is in constant proportion to bias current in the first transistor and first resistor. Output impedance can be made positive, negative or zero by appropriate proportioning of the first and second resistors.

Patent
Anil Gupta1, Kuo-Lung Chen1
08 Mar 1993
TL;DR: In this article, a two-transistor flash EPROM cell includes a first floating gate transistor for programming the cell and a second merged transistor for reading the cell, and the merged transistor effectively consists of a floating-gate transistor in series with a NMOS enhancement transistor.
Abstract: A two-transistor flash EPROM cell includes a first floating gate transistor for programming the cell and a second merged transistor for reading the cell. The first transistor, a floating gate transistor, has a drain coupled to the write bit line, a gate coupled to the word line, and a source coupled to the source line. The merged transistor effectively consists of a floating gate transistor in series with a NMOS enhancement transistor. The series NMOS transistor has a voltage threshold of about 1 to 2 volts, thus preventing cell activation caused by overerasure (negative voltage threshold) of the floating gate transistor.

Patent
Kenji Tsuchida1, Takashi Ohsawa1
28 May 1993
TL;DR: In this paper, a MOS dynamic random access memory device has a memory cell array section formed on a semiconductor substrate, including memory cells each having a data storage capacitor and a transfer-gate transistor.
Abstract: A MOS dynamic random access memory device has a memory cell array section formed on a semiconductor substrate, including memory cells each having a data storage capacitor and a transfer-gate transistor. Parallel bit lines are associated with the memory cell array section. Parallel word lines extend transverse to the bit lines, including a word line connected to the transfer-gate transistor. A booster circuit is arranged to provide a potentially raised voltage which is higher than a power supply voltage. A sense amplifier circuit is connected with a corresponding bit line pair of the word lines. A word-line driver circuit has an input connected to the booster circuit and an output connected to the word line. A bit-line restoring circuit is connected to the sense amplifier circuit. The restoring circuit includes a voltage-down converting metal oxide semiconductor field effect transistor having an insulated gate connected to the booster circuit, a drain coupled to the power supply voltage, and a source at which a potentially decreased voltage appears to be lower than the power supply voltage. The voltage-down converting transistor is same in channel conductivity type as the transfer-gate transistor.

Patent
17 Sep 1993
TL;DR: In this article, a device integrated on a chip of a semiconductor material is disclosed which comprises an NPN bipolar transistor (T2) and an N-channel MOSFET transistor in an emitter switching configuration, both being vertical conduction types.
Abstract: A device integrated on a chip of a semiconductor material is disclosed which comprises an NPN bipolar transistor (T2) and an N-channel MOSFET transistor (T3) in an emitter switching configuration, both being vertical conduction types. The bipolar transistor (T2) has its base (13) and emitter (14) regions buried; the MOSFET transistor (T3) is formed with an N region (16) bounded by the base (13) and the emitter (14) regions and isolated by a deep base contact and isolation region (15). To improve the device performance, especially at large currents, an N+ region (17) is provided which extends from the front of the chip inwards of the isolated region (16) and around the MOSFET transistor (T3). In one embodiment of the invention, a MOSFET drive transistor (T1) is integrated which has its drain terminal in common with the collector (C) of the bipolar transistor (T2), its source terminal connected to the base of the bipolar transistor (T2), and its gate electrode connected to the gate electrode (G) of the MOSFET transistor (T3) in the emitter switching configuration.

Patent
30 Jul 1993
TL;DR: In this paper, the authors present a CMOS amplifier with two legs, each of which includes an input transistor, which is biased to the desired common mode voltage and has a gate connected to a voltage corresponding to the means voltage of the output stage.
Abstract: In a CMOS amplifier having a differential input and differential output, the input stage includes two legs, each of which includes an input transistor. A common mode negative feedback stage includes a load connected to the high supply voltage, a first transistor connected between the load and a common terminal of the input transistors. The first transistor is biased to the desired common mode voltage. A second transistor is connected between the load and the low supply voltage, and has a gate connected to a voltage corresponding to the means voltage of the output stage. An additional transistor is disposed in parallel with each input transistor. Each additional transistor has its gate connected to the desired common mode voltage.

Patent
04 Feb 1993
TL;DR: In this paper, a non-self aligned implanted channel is proposed for a high voltage CMOS transistor with an accurate insertion into the gate electrode of the device through direct wafer stepper technology.
Abstract: A process for fabricating a high voltage CMOS transistor having a non-self aligned implanted channel which permits the operation of the device at high voltages. The non-self aligned implanted channel does not require alignment with the gate electrode of the CMOS device, but is accurately implanted early in the fabrication of the device through reliance on direct wafer stepper technology. As a result, the non-self aligned implanted channel does not require a high temperature drive, such that fabrication of the transistor is compatible with VLSI and ULSI processes, and the transistor can be up-integrated onto logic integrated circuits. Accuracy of the placement of the non-self aligned implanted channel provides for a shorter channel length, which enables the device to be highly area efficient while also increasing the current capability of the device. Furthermore, the transistor is characterized by a large field-induced avalanche breakdown voltage, enhanced by a thick gate oxide, a lightly doped drain, a field oxide region between the gate and the drain, and known field plating techniques.

Patent
08 Sep 1993
TL;DR: In this paper, a circuit in which the source-to-drain conduction path of a power switching transistor (N1) is connected in series with an inductive load (L1) between first and second power terminals is described.
Abstract: A circuit in which the source-to-drain conduction path of a power switching transistor (N1) is connected in series with an inductive load (L1) between first and second power terminals and includes a voltage transient clamping transistor (P1) having its source-to-drain conduction path connected between the drain and gate of the switching transistor (N1). In response to a turn-off signal applied to the gate of the switching transistor (N1), a transient voltage is generated at the drain of the switching transistor and when the transient voltage exceeds a predetermined value, the clamping transistor (P1) is turned on. The conduction of the clamping transistor (P1) limits the voltage rise at the drain of the switching transistor (N1) and tends to maintain the switching transistor (N1) conductive to aid in the discharge of the energy stored in the inductive load (L1). A unidirectional conducting element connected in series with the clamping transistor (P1) ensures that only current of a polarity to discharge the inductive load (L1) flows through the clamping transistor (P1).

Patent
William Liu1
12 Nov 1993
TL;DR: In this article, a method for fabricating a transistor having a plurality of active regions comprising spacing or shaping the emitters 20 and 22, or gates, in a non-uniform manner to provide a substantially constant temperature over an active region of the transistor is disclosed.
Abstract: Generally, and in one form of the invention, a method for fabricating a transistor having a plurality of active regions comprising spacing or shaping the emitters 20 and 22, or gates, in a non-uniform manner to provide a substantially constant temperature over an active region of the transistor is disclosed. An advantage of the invention is that the occurrence of a thermal runaway condition between transistor current and temperature is generally avoided.

Patent
Koji Hamada1
08 Nov 1993
TL;DR: In this paper, a drain offset region is formed between a channel region and a drain region in a polycrystalline silicon thin film transistor, and a sub-gate structure comprises at least one sub gate, except for a main gate which is provided in a normal field effect transistor.
Abstract: A novel structure of a polycrystalline silicon thin film transistor manifested in a drain offset region and a sub-gate structure. The drain offset region is formed between a channel region and a drain region in the polycrystalline silicon thin film. The sub-gate structure comprises at least one sub-gate, except for a main gate which is provided in a normal field effect transistor. This structure is applicable to either an upper gate type or a bottom gate type thin film transistor. The sub-gate structure may include an upper sub-gate and/or a bottom sub-gate. The upper sub-gate overlays the channel region, drain offset and drain regions through an insulation layer. The bottom sub-gate underlies the channel region, drain offset and drain regions through an insulation layer. The sub-gate is applied with the same voltage or less as the drain voltage thereby permitting a relaxation of a high field concentration caused at a drain junction to be realized. This may provide a reduction of a leakage current and a security of a high ON-current.

Patent
Baoson Nguyen1
30 Apr 1993
TL;DR: In this article, a bandgap voltage reference (V BG) is generated by a current squaring circuit (CSC) and a sampling current signal (I SC) generated in a current generator amplifier.
Abstract: A bandgap reference circuit (14) in a bandgap voltage reference device (10) generates a bandgap voltage reference (V BG ) at the base of a Q1 transistor (22) and a Q2 transistor (20). A reference current signal I T flows into the collectors of the Q2 transistor (20) and the Q1 transistor (22) as generated by a difference in base to emitter voltages due to a difference in emitter areas between the Q2 transistor (20) and the Q1 transistor (22). A correction current signal (I TT ) generated by a current squaring circuit (16) is injected into the collector of the Q1 transistor (22) such that the collectors of the Q2 transistor (20) and the Q1 transistor (22) have unequal current values. The current squaring circuitry (16) generates the correction current signal (I TT ) by squaring the reference current signal (I T ) and dividing it into a sampling current signal (I SC ) generated in a current generator amplifier (18). The collector current difference between the Q2 transistor (20) and the Q1 transistor (22) enable the elimination of the second order temperature coefficient, as well as the first order temperature coefficient, of the base to emitter voltage (V BE ) Of the Q1 transistor (22). In this manner, a bandgap voltage reference (V BG ) becomes more stable, accurate, and less temperature dependent.

Journal Article
A.A. Grinberg1, Serge Luryi1
TL;DR: In this paper, the authors considered the high-frequency operation of an abrupt-heterojunction transistor with ballistic transport in the base, and the unilateral gain U calculated for an exemplary heterostructure, including the parasitics, demonstrates an active behavior of the coherent transistor in extended frequency ranges.
Abstract: The high-frequency operation of an abrupt-heterojunction transistor with ballistic transport in the base is considered. The coherent regime arises at temperatures low enough compared to the injection energy that the injected minority carriers form a nearly collimated and monoenergetic beam. The coherent transistor can have both current gain and power gain at frequencies far above the conventional cutoff. The extended frequency of an intrinsic transistor is limited by the dispersion in the minority-carrier times of flight across the base, rather than the average time of flight itself. The unilateral gain U calculated for an exemplary heterostructure, including the parasitics, demonstrates an active behavior of the coherent transistor in extended frequency ranges. >

Patent
14 Jun 1993
TL;DR: In this article, a self-aligned static induction transistors are fabricated using a single minimum geometry trench mask and the key features of the transistor are defined by the trench masks and related processing parameters.
Abstract: A method of fabricating self aligned static induction transistors. The method comprises fabricating an N silicon on N⁻ silicon substrate having an active area. A guard ring is formed around the active area. An N⁺ polysilicon layer is formed that comprises source and gate regions. An oxide layer is formed on the N⁺ polysilicon layer. A second polysilicon layer is formed on the oxide layer. A second oxide layer is formed on the second polysilicon layer which is then masked by a self aligning mask. Trenches are etched into the substrate using the self aligning mask and gate regions are formed at the bottom of the trenches. A first layer of metal (gate metal) is deposited to make contact with the gate regions. A layer of photoresist is deposited and planarized, and the first layer of metal is overetched below the top surface of the trench. Plasma nitride is deposited and planarized, and a polysilicon mask is deposited over the planarized layer of plasma nitride. The polysilicon mask is etched to expose the gate metal disposed on the field. A second layer of metal is deposited to make contact with the source and gate regions. A passivation layer is formed, and interconnection pads are formed that connect the first and second layers of metal. The present method employs a single minimum geometry trench mask. The key features of the transistor are defined by the trench mask and related processing parameters. Because of the self alignment achieved by the present invention, the number of channels per unit area is higher, which results in higher transconductance. In addition, some of the parasitic capacitance is eliminated by the present invention, resulting in faster operational speed. The variable sidewall trench oxide thickness allows fabrication of static induction transistors with higher or lower breakdown voltages according to the thickness that is chosen, and for a more graded P gate junction.