Showing papers on "Static induction transistor published in 1994"

Series-parallel association of FET's for high gain and high frequency applications

Abstract: This paper presents a simple approach in the design of composite field effect transistors with low output conductance. These transistors consist of the series association of two transistors, with the transistor connected to the drain terminal wider than the transistor connected to the source terminal. It is shown that this composite transistor has the same DC characteristics as a long-channel transistor of uniform width. A composite transistor has two main advantages over its "DC equivalent" transistor of uniform width: significant area savings and a higher cutoff frequency. The main application is low-voltage, high-frequency analog circuits. The proposed technique is particularly suited for analog design in gate arrays. >

VDMOS transistor and manufacturing method therefor

Abstract: A VDMOS transistor having a reduced drain/source resistance without a corresponding decrease in breakdown voltage and a manufacturing method therefor. Such a VDMOS transistor is created by gradually increasing the doping density of the transistor's implanted regions, while simultaneously increasing the respective thicknesses of the gate oxide layers corresponding to the implanted regions along the current flow path.

Electrical model of the floating gate defect in CMOS ICs: implications on I/sub DDQ/ testing

Abstract: The behavior of an MOS transistor with an open in the polygate path (floating transistor gate defect) is investigated and its effect on the quiescent power supply current I/sub DDQ/ is studied. The possible detection of this defect by current testing is explored in fully complementary CMOS circuits. The behavior of a transistor with its floating gate is modeled using the coupling capacitances in the floating gate and the charge in the transistor gate. The poly-bulk and metal-poly capacitances are found to be two significant parameters in determining the degree of conduction on the affected transistor. The induced voltage in the floating gate and the quiescent current are estimated by analytical expressions. The model is compared with SPICE 2 simulations. Good agreement is observed between the simple analytical expressions, simulations and experimental measures performed on defective circuits. In addition, it is shown that the floating gate transistor can be modeled as a weakly conductive stuck-on transistor or as a stuck-open transistor depending on the values of the parameters characterizing the defect. >

The all-metal spin transistor

Abstract: An entirely new kind of switching device is fabricated entirely from metals. The three-layer, three-terminal spin transistor behaves somewhat like a semiconductor bipolar transistor; though the physical operating principles differ. The emitter and collector layers of the spin transistor are ferromagnetic films. The base layer is a nonmagnetic metal, such as gold, copper, or silver. Being all-metal the device can be made much smaller than semiconductor transistors-less than 0.1 micrometer on a side. Although still a technological infant, the device has the electrical properties required by memory cells, current amplifiers, and logic circuits. A computer made only of metals seems quite possible. >

Characterization of subthreshold MOS mismatch in transistors for VLSI systems

Abstract: MOS transistor mismatch is revisited in the context of subthreshold operation and VLSI systems. We report experimental measurements from large transistor arrays with device sizes typical for digital and analog VLSI systems (areas between 9 and 400μm2). These are fabricated at different production qualified facilities in 40-nm gate oxide,n-well andp-well, mask lithography processes. Within the small area of our test-strips (3 mm2), transistor mismatch can be classified into four categories: random variations, “edge,” “striation,” and “gradient” effects. The edge effect manifests itself as a dependence of the transistor current on its position with reference to the surrounding structures. Contrary to what was previously believed, edge effects extend beyond the outer most devices in the array. The striation effect exhibits itself as a position-dependent variation in transistor current following a sinusoidal oscillation in space of slowly varying frequency. The gradient effect is also a position-dependent spatial variation but of much lower frequency. When systematic effects are removed from the data, the random variations follow an inverse linear dependence on the square root of transistor area.

Phase clocked shift register with cross connecting between stages

Abstract: A shift register for scanning a liquid crystal display includes cascaded stages. A given stage is formed with an input transistor switch that is responsive to an output pulse of a stage upstream in the chain of the cascaded stages. The input transistor switch charges a capacitance associated with a control electrode of a switched pull-up output transistor. The voltage in the capacitance conditions the output transistor for generating an output pulse when subsequently a clock signal occurs to the output transistor. A clamping transistor discharges the capacitance in a manner to prevent further generation of the output pulse when subsequent pulses of the clock signal occur. The clamping transistor is responsive to an output pulse of a stage downstream in the chain. An impedance that is developed at the control electrode is substantially higher after the clamping operation occurs and remain high for most of the vertical interval.

Output driver circuit with body bias control for multiple power supply operation

Abstract: A push-pull output driver including two transistors in series, one transistor having its body bias controlled by logic circuitry commanded by the driver input. The driver has a pair of transistors in series, the transistor inputs being complementary to create a push-pull amplifier. A switching transistor is controlled by the inverse of the driver input signal and acts as a switch at the pull-up transistor well-tie. When the driver input is high, the switching transistor is off allowing the well-tie to the pull-up transistor to be connected to the driver output. When the input is low, the switching transistor turns on, switching the well-tie of the pull-up transistor to ground. By controlling the body bias of the pull-up transistor in this way, the switching speed of the output driver is significantly increased. When the output driver is in a disabled tri-state mode, the series transistors, and the switching transistor, are turned off. A first deselect transistor provides a high voltage at the drain of a load transistor to force it into cutoff. A select transistor is turned off to isolate the pull-up transistor well-tie from the output node, and a second deselect transistor is switched on to connect it to ground. This embodiment isolates the well-tie from the driver output while in tri-state to prevent latch-up initiated by multiple power supply operation.

Method for making heterojunction bipolar transistor with self-aligned retrograde emitter profile

Abstract: A high gain, high frequency transistor is formed having a combination of a moderately doped retrograde emitter and a collector which is formed by self-aligned implantation through an emitter opening window. This combination allows continued base width scaling and ensures high current capability yet limits the electric field at the emitter-base junction, particularly near the base contacts, in order to reduce leakage and capacitance and to enhance breakdown voltage. Cut-off frequencies on the order of 100 GHz can thus be obtained in the performance of a transistor with a 30 nm base width in a SiGe device.

High-performance insulated-gate field-effect transistor

Abstract: An improved device fabrication method and transistor structure 36 provide shallow, heavily doped, source/drain junction regions 64 and a uniformly doped lower gate region 50 having a high concentration of dopants efficiently distributed near the gate electrode/gate interface 51. The gate, source, and drain terminals of transistor 36 may be interconnected to other neighboring or remote devices through the use of reacted refractory metal interconnect segments 98 and 100. Transistor structure 36 of the present invention may be constructed in an elevated source/drain format to include elevated source/drain junction regions 87 which may be fabricated simultaneous with a primary upper gate electrode region 88. This elevated source/drain junction feature is provided without added device processing complexity.

3.3 volt CMOS tri-state driver circuit capable of driving common 5 volt line

Abstract: A CMOS tri-state driver circuit is capable of operating in a normal drive mode and in a high impedance mode. The circuit is powered by a 3 volt power supply, and drives an output terminal that is common to a TTL or other device that can apply a 5 volt output to the output terminal. The circuit includes a PMOS pull-up transistor and an NMOS pull-down transistor that are connected to the output terminal. The pull-up transistor is formed in and has a substrate terminal that is connected to an N-well. A switching transistor is controlled to connect the N-well to the power supply in drive mode to ensure stable and strong pull-up drive. A pass-gate transistor is biased to turn off the switching transistor when the voltage at the output terminal is higher than the power supply voltage in high impedance mode, causing the N-well to float. This prevents leakage current from flowing through a semiconductor junction from the output terminal to the N-well through the pull-up transistor. A shorting transistor is controlled to short the gate of the pull-up transistor to the N-well when the voltage at the output terminal is higher than the power supply voltage in high impedance mode, thereby preventing leakage current from flowing through the channel of the pull-up transistor.

Storage cell using low powered/low threshold CMOS pass transistors having reduced charge leakage

Abstract: A storage cell includes a first bit line, a storage circuit, and a pass transistor. The storage circuit has a first storage node for holding a logic state indicative of a logic value. The pass transistor is coupled to the first bit line and the first storage node for establishing a conduction path therebetween. The pass transistor receives a bias voltage to switch the pass transistor into a substantially nonconducting state when the storage cell is not being accessed. The reverse bias on the first transistor substantially reduces the leakage current through the pass transistor.

Method for manufacturing a VDMOS transistor

Abstract: A VDMOS transistor having a reduced drain/source resistance without a corresponding decrease in breakdown voltage and a manufacturing method therefor. Such a VDMOS transistor is created by gradually increasing the doping density of the transistor's implanted regions, while simultaneously increasing the respective thicknesses of the gate oxide layers corresponding to the implanted regions along the current flow path.

Process for fabricating a complementary MIS transistor

Abstract: A CMIS transistor suitable for device miniaturization, elimination of degradation of operational characteristics by hot carrier effect, and elimination of decrease of threshold voltage caused by short channel effect, includes a laterally spreading N-type diffusion region having an impurity concentration level higher than P-type and N-type wells but lower than source and drain regions, such that the N-type diffusion region extends laterally into a part located immediately below an edge of an insulating gate and has a depth smaller than a depth of the source and drain regions. The device is thereby capable of increasing the width of depletion layer at the bottom of the source and drain regions while maintaining effectiveness as a punch-thorough stopper. Thereby, the junction capacitance at the source and drain regions is reduced and the operational speed of the device improved in the P-channel transistor part in the device. In the N-channel transistor part, an effective suppression of punch-through is achieved because of the small diffusion depth of the N-type diffusion region. Thereby, the decrease of threshold voltage caused by the short channel effect is effectively eliminated even when the gate length of the transistor is reduced.

Semiconductor device having a protective transistor

Abstract: A semiconductor device has an internal circuit, an output transistor and a protective transistor for protecting the output transistor and the internal circuit against an ESD-induced destruction caused by a surge pulse entering from an input/output terminal. The sum of a first distance between a contact for connecting an input/output terminal with the collector of the protective transistor and a field oxide film and a second distance between a contact for connecting the input/output terminal with the emitter of the protective transistor and the field oxide film overlying the base of the laterally formed protective transistor is made smaller than the sum of a third distance between a contact for connecting the input/output terminal with the drain of the output transistor and the gate electrode of the output transistor and a fourth distance between a contact for connecting a potential line with the source of the output transistor and the gate electrode of the output transistor. Besides, the effective channel length of the output transistor is made longer than the effective base width of the protective transistor.

Electrically erasable programmable non-volatile semiconductor memory device having select gates and small number of contact holes

Abstract: The structure of the invention employs a lamination type memory cell and a lamination type select transistor having a floating gate. Since no contact holes are formed in a first polysilicon film of a high resistance, it is not necessary to form a contact hole in the gate wire of the select transistor between a cell array. A floating gate is beforehand charged with electricity so that the select transistor cab have a positive threshold value. Alternatively, an impurity is introduced into the channel region of the select transistor so that the neutral threshold voltage of the transistor after radiation of ultraviolet rays can have a positive value.

Vertical field-effect transistor and a semiconductor memory cell having the transistor

Abstract: The disclosure includes a vertical field-effect transistor (115) with a laterally recessed channel region (92), a vertical field-effect transistor (116) having a graded diffusion junction (31), a static random access memory cell (110) having a vertical n-channel field-effect transistor (116) and a vertical p-channel field-effect transistor (115) and methods of forming them. In one embodiment, a six-transistor static random access memory cell (110) has two pass transistors (111 and 114), which are planar n-channel field-effect transistors, two latch transistors (113 and 116), which are vertical n-channel field-effect transistors with drain regions having graded diffusion junctions (31), and two load transistors (112 and 115), which are vertical p-channel thin-film field-effect transistors having laterally recessed channel regions (92).

Method and apparatus for short circuit protection of power transistor device

Abstract: A circuit and method for detecting and protecting against an overcurrent condition in a power transistor switching device, and particularly an IGBT. The power transistor switching device has main terminals and a control terminal, the main terminal having a normal saturation voltage therebetween during normal conduction of the power transistor device. The circuit includes a driver providing control signals to the control terminal of the power transistor device for switching the power transistor device on and off, a sensing circuit coupled to the power transistor device for sensing the saturation voltage of the power transistor device, and a switching circuit coupled to the control terminal of the power transistor device and responsive to the sensing circuit for removing the control signals from the control terminal in the event the saturation voltage reaches an abnormal level indicating an overcurrent condition in the power transistor device.

N-channel voltage regulator

Abstract: A power-efficient power regulation circuit for use in semiconductor circuit powered by a power signal includes an N-channel transistor which provides a regulated power signal having a stabilized voltage level for use by the semiconductor circuit. A bias pull-up circuit is coupled to the gate of the N-channel transistor and arranged for biasing the N-channel transistor so that it normally conducts current, and a resistive circuit, including a resistive element arranged in series with a resistor-arranged P-channel transistor, is coupled to the source of the N-channel transistor and, in response to the regulated power signal, provides a feedback control signal. A voltage control circuit, coupled to the bias pull-up circuit and the resistive circuit, is activated to control the N-channel transistor in response to the feedback control signal. The voltage control circuit may include an enabling transistor which is activated to enable the voltage control circuit.

Over-current protection apparatus for transistor

Abstract: The disclosed invention is designed to prevent the oscillation which often occurs in an over-current protection apparatus for an insulated gate controlled transistor. The apparatus improves the response in current detection, to prevent oscillation, and improves protection speed against over-current. This is accomplished by separating the gates of the main transistor and the current detector transistor; by setting a shorter time constant for the gate circuit of the current detector transistor than that of the gate circuit of the main transistor; by feeding the detection signal obtained from the current detecting means which detects the current i of the current detector transistor proportional to the current I flowing through the main transistor, to the control means; and by controlling the gate potentials of both transistors to protect the main transistor from the over-current by feeding the comparison output Sd from the comparator circuit, which compares the voltage of the signal Vd with the reference voltage Vr, to the control circuit.

Circuit arrangement with a field-effect transistor

Abstract: Circuit arrangement having a FET (Field Effect Transistor), wherein the FET comprises a drain, gate and source, and means with which the gate is charged and discharged, and other high-rate discharge means with which the gate is discharged, wherein said quick discharge means - from the drain voltage of the FET (1) are controlled and - connect the gate of the FET (1) having a potential, wherein a first switch (11, 20) and a second switch (10, 21, 23) is arranged between the gate of the FET (1) and the potential, wherein the second switch (10, 21, 23) from the drain voltage of the FET (1) is driven, characterized, in that the gate of which is driven by a constant voltage source, a high voltage FET is arranged between the second switch and the drain of the FET (1).

Power driver circuit with reduced turnoff time

Abstract: This application discloses circuit and method for reducing the turn-off time of a power transistor driving an inductive load. The circuit clamps the gate to source of a power transistor by using two field effect transistors as the current path across the gate and source of the power transistor. A zener diode connected from the source to gate of the two field effect transistors is used to provide high voltage protection.

N-stage ring connected voltage controlled oscillator

Abstract: A VCO includes an oscillator and a controller for controlling the operation of the oscillator. The oscillator is formed by connecting odd number of stages of delay circuits in a ring form. The controller creates a second control voltage based on an input first control voltage. The second control voltage is set in a symmetrical relation to the first control voltage with respect to an intermediate potential between the power supply and the ground set as a reference. Each of the delay circuits includes an inverter, first and second current control circuits, and first and second current value setting circuits. The inverter includes a first transistor of first conductivity type and a second transistor of second conductivity type to receive and output a signal. The first current control circuit is connected between the first transistor and the ground, for controlling a current flowing in the first transistor when the first transistor is set in the conductive state according to the first control voltage. The first current value setting circuit sets the minimum value of the current flowing in the first transistor. The second current control circuit is connected between the second transistor and the power supply, for controlling a current flowing in the second transistor when the second transistor is set in the conductive state according to the second control voltage. The second current value setting circuit sets the minimum value of the current flowing in the second transistor.

Method and apparatus for a two phase bootstrap charge pump

Abstract: An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and drain terminals of all other stages, a second N type field effect control transistor device having drain and source terminals connecting the drain terminal and the gate terminal of the first switching transistor device, and a storage capacitor joined to the source terminal of the first device; a source of voltage to be pumped is connected to the drain terminal of the first device of the first stage. A first series of clock pulses is applied to the gate terminals of the first switching transistor devices in every other stage of the charge pump and to the gate terminals of the second control transistor devices in stages between; and a second series of clock pulses which do not overlap the first series of clock pulses is applied to the gate terminals of the first switching transistor devices in alternate stages of the charge pump and to the gate terminals of the second control transistor devices in stages between the alternate stages. These pulses cause the switching transistor to switch on and off in alternate stages in a manner that the gate terminal goes higher than the drain terminal so that charge is transferred without threshold drop between stages and high current as well as high voltage is pumped to the output terminal.

Field effect transistor with switchable body to source connection

Abstract: To avoid forward biasing the diodes within an N-channel transistor, the body (36) and source (38) of the N-channel transistor (34) are switchably connected via a high-voltage FET (42). The gates (46, 50) of the N-channel transistor (34) and high-voltage transistor (42) are connected together so that both transistors are on or off simultaneously. When both transistors are on, the high-voltage transistor (42) shorts the body (36) and source (38) of the N-channel transistor (34). When both transistors are off, the body (36) and source (38) of the N-channel transistor (34) are disconnected and a third transistor (56) couples the body to a reference potential. The N-channel transistor (34) and high voltage transistor (42) share a common body in a semiconductor substrate. The source (38) of the N-channel transistor (34) provides an output terminal for the circuit. A number of these devices, each connected to a different supply voltage, can be connected to the same output terminal and selectively energized to form a voltage multiplexer.

Thin film transistor protection circuit

Abstract: A thin film transistor protection circuit includes a outer short-circuit line formed around a pixel electrode driving thin film transistor on an array substrate, and a discharging thin film transistor having a gate electrode and a current path connected between a wiring line connected to the pixel electrode driving thin film transistor and the outer short-circuit line The protection circuit further includes a charging circuit for charging the gate electrode of the discharging thin film transistor according to a difference in potential between the conductive and wiring lines

DC biasing and AC loading of high gain frequency transistors

Abstract: A small sized energy conveying and signal dissipating loading apparatus for use in the testing of a transistor of the high gain high frequency type is disclosed. The energy conveying and loading device of the invention employs a transmission line-like network of distributed components in order to roll off and dampen or dissipate the high frequency alternating current response of the transistor under test while also being electrically invisible for measuring the low frequency or DC characteristics of the transistor under test. The described energy communicating and loading apparatus is compatible with the temperatures of a test environment for even the most extreme environment transistor devices and allows convenient placement in the test environment immediately adjacent the transistor under test. The load allows testing of multiple transistor devices with reasonable space and cost requirements. Use of the energy communicating and loading invention with a hetrojunction bipolar transistor of the microwave type and in conjunction with discrete bypass capacitors are also disclosed.

A control circuit with a level shifter for switching an electronic switch

Abstract: A control circuit for a power transistor, connected between two supply terminals in series with a load. The control circuit comprises a control logic circuit which produces a signal at two levels with respect to a reference terminal, a level shifter connected between the control circuit and the power transistor, which produces a signal at two levels relative to the node between the power transistor and the load. The level shifter comprises a flip-flop the output of which controls the power transistor, and an electronic switch, for example a MOSFET transistor, connected between the "set" input of the flip-flop and the node and controlled by the "reset" input of the flip-flop in such a way as to be closed when the "reset" input is greater, by a predetermined value, than that of the node. The electronic switch prevents the parasitic current flowing through the set and reset inputs from erroneously switching the power transistor.

Constant impedance sampling switch for an analog to digital converter

Abstract: A constant impedance sampling switch suitable for a high-frequency analog-to-digital converter, presents a substantially constant impedance to the input signal regardless of the instantaneous level of the input signal. The exemplary sampling switch employs a single metal oxide semiconductor (MOS) transistor to selectively couple the input signal to a sampling circuit. The gate signal for this transistor is generated by circuitry which is disconnected from the gate of the transistor while the transistor is in an non-conductive state. During a sampling interval, the gate signal is boot-strapped by the instantaneous potential of the input signal to render the transistor conductive. Accordingly, the potential difference between the signal being sampled and the gate potential of the transistor remains substantially constant over a relatively wide range of amplitudes for the analog input signal.

Device and method for high performance high voltage operation

Abstract: A high voltage device (10) having MOS input characteristics. A low voltage MOS transistor (12) is provided which has a source (18), a drain (22), and a gate (25). A high voltage transistor (14) is also provided which has a source (20), a drain (24), and gate (16). The source (18) of the low voltage MOS transistor (12) is connected to the gate (16) of the high voltage transistor (14). The drain (22) of the low voltage MOS transistor (12)is connected to the source (20)of the high voltage transistor The low voltage MOS transistor (12) may have a silicon substrate and the substrate of the high voltage transistor (14)may comprise silicon, silicon carbide, or gallium arsenide.