Showing papers on "Static induction transistor published in 1997"

Semiconductor device including active matrix circuit

Abstract: There is provided a combination of doping process and use of side walls which allows the source and drain of a thin film transistor of an active matrix circuit to be doped with only one of N-type and P-type impurities and which allows the source and drain of a thin film transistor used in a peripheral circuit of the same conductivity type as that of the thin film transistor of the active matrix circuit to include both of N-type and P-type impurities. Also, a thin film transistor in an active matrix circuit has offset regions by using side walls, and another thin film transistor in a peripheral circuit has a lightly doped region by using side walls.

Pass gate circuit with body bias control

Abstract: A pass gate circuit includes a pass transistor and a body bias control circuit for biasing the body of the pass transistor to reduce body effect. The body bias control circuit includes one or more control transistors arranged to selectively connect the substrate (body) of the pass transistor to the drain or gate of the pass transistor when predetermined voltages are applied to the drain and gate of the pass transistor. As a result, the pass transistor exhibits a reduced body effect in the on-state. In one embodiment, the body bias control circuit includes a first control transistor having a drain and gate connected to the gate of the pass transistor, a gate connected to the drain of the pass transistor, and a source. The body bias control circuit also includes a second control transistor having a drain connected to the source of the first control transistor, a source connected to a body of the pass transistor, and a gate connected to the drain of the pass transistor. The bodies of the pass transistor, first control transistor and second control transistor are electrically interconnected. With this arrangement, the body of the pass transistor is biased "high" by the gate of the pass transistor only when both the gate and drain of the pass transistor are at a high voltage level.

Full-wave rectifier and method of operation for a recognition system

Abstract: A full-wave rectifier circuit (70) includes a first transistor (N1) and a second transistor (N2) in combination to form a first transistor pair (N1 and N2) for minimizing the voltage drop between ground (88) and the transponder substrates. A third transistor (P1) and a fourth transistor (P2) operate in combination to form a second transistor pair (P1 and P2) for minimizing the voltage drop between the alternating current peak voltage (118 and 120) and the output voltage (VDD) of the full-wave rectifier (70). The first transistor pair (N1 and N2) and second transistor pair (P1 and P2) are controlled by alternating current voltage input signals (118 and 120). A series regulator circuit (70) decouples the first transistor pair (N1 and N2) and the second transistor pair (P1 and P2) from capacitive loads (C1 and C2) of the full-duplex transponder circuitry (14).

Fabrication method for sub-half micron CMOS transistor

Abstract: A technique for forming a high-performance sub-half micron MOS transistor is disclosed which has improved short channel characteristics without degradation of device performance. The transistor comprises a semiconductor substrate, a gate electrode, graded source and drain impurity regions, a first set of gate sidewall spacers, and a second set of gate sidewall spacers. The graded source and drain impurity regions comprise a relatively linear continuum of doped regions, ranging from lightly doped (LDD) regions, to moderately doped (MDD) regions, to heavily doped regions. Additionally, the transistor may include a punch through barrier region located within the substrate under the gate electrode. With these features, the transistor of the present invention allows for more precise control of conduction channel length without degradation of either (1) body factor and current drive, and/or (2) junction leakage, and without compromising hot carrier immunity.

Circuit and method for driving an organic light emitting diode (O-LED) display

Abstract: Disclosed is a technique for driving a column of pixels implemented using O-LEDs. The technique includes separate, digitally adjustable current sources on each column conductor of the array. For each column, the digitally-programmed current flow terminates with a reference O-LED and a series NMOS transistor forming the input leg of a novel, distributed current mirror. The current is "mirrored" to the output leg of the distributed current mirror which can service any one of a plurality of active O-LEDs in the column based on a row select signal. In this way, a transistor on the output leg of the current mirror couples its respective O-LED to a source of operational power. The mirrored charge on the gate of the output leg transistor causes it to apply the same current to the active O-LED as was applied to the reference O-LED through the input leg transistor. Additionally, the voltage drop across the NMOS transistor and the reference O-LED is used to charge a capacitor associated with the selected O-LED. The charging of the capacitor, as a result of the digitally-programmed current supplied through the NMOS transistor to the reference O-LED, allows for continuous driving of the active O-LED during a cycle through. Thus, a reference O-LED in conjunction with an NMOS transistor, services all of a plurality of sequentially-loaded rows within each column.

Multi-state flash memory cell and method for programming single electron differences

Abstract: A flash memory cell. The cell includes a transistor with a floating gate that is formed from a number of crystals of semiconductor material. The crystals are disposed in the gate oxide of the transistor. The size of the crystals and their distance from a surface of a semiconductor layer of the transistor are chosen such that the crystals can trap a single electron by hot electron injection. Each trapped electron causes a measurable change in the drain current of the transistor. Thus, multiple data bits can be stored and retrieved by counting the changes in the drain current.

Sense amplifier for high-density imaging array

Abstract: A sense amplifier comprises an input node and an output node. An input transistor has a gate connected to the input node, a source connected to a first supply voltage rail, and a drain. A cascode transistor has a gate connected to a cascode node, a source connected to the drain of the input transistor, and a drain connected to the output node. A load transistor has a gate connected to a bias node, a drain connected to the output node, and a source connected to a second supply voltage rail. The gates of the cascode transistor and the load transistor are biased such that the input transistor and the cascode transistor are operated near their threshold and the load transistor is operated above threshold. In a presently preferred embodiment of the present invention, the input transistor and the cascode transistor of the sense amplifier are wide and short, such that they operate in below threshold, whereas the load transistor is made long and relatively narrow, so that it operates above threshold.

Device and method of manufacture for protection against plasma charging damage in advanced MOS technologies

Abstract: A protection device which protects against charge build up on a thin oxide gate during plasma etching is provided. The protection device may be described as a floating well PMOS device. When the PMOS transistor is formed, a lateral parasitic pnp transistor is also formed. In the lateral pnp device the base is floating, the collector is connected to ground and the emitter is connected to the gates of the host PMOS protection device and the device to be protected. In operation, the gate of the PMOS transistor is tied to the source of the PMOS transistor so that the PMOS transistor is off. Thus, the lateral pnp transistor controls the charging and discharging of the charge stored on the gate oxide. Excessive charge build up is prevented by the breakdown voltage of the lateral pnp transistor. Because protection is achieved by pnp breakdown operation, the size of the pnp protection device can be substantially lower than other protection devices.

Structure for increasing the maximum voltage of silicon carbide power transistors

Abstract: A silicon carbide insulated gate power transistor is disclosed that demonstrates increased maximum voltage. The transistor comprises a field effect or insulated gate transistor with a protective region adjacent the insulated gate that has the opposite conductivity type from the source for protecting the gate insulator material from the degrading or breakdown effects of a large voltage applied across the device.

Field effect transistor and CMOS element having dopant exponentially graded in channel

Abstract: A field effect transistor is fabricated on an SOI substrate. N-type source and drain regions are arranged apart from each other in a semiconductor thin film of the SOI substrate. A P-type channel region is formed between the source and drain regions. Moreover, a gate electrode is formed over the channel region to cover the channel region through a gate oxide film. Extreme portions of the channel region, adjacent to the source and drain regions, have higher doping concentrations than in a center portion thereof. Furthermore, the gradient of the doping profile in the channel region is adjusted so as to reduce the current gain of a parasitic transistor in the field effect transistor. This structure enables a reduction of the channel length of the field effect transistor to the sub-half-micron order without deteriorating the electrical characteristics of the field effect transistor.

Vertical transistor and memory cell

Abstract: A method for manufacturing a three-dimensionally structured vertical transistor or memory cell forms a silicon-on-insulator (SOI) structure on a semiconductor substrate and sequentially deposits a drain region, a channel region and a source region on the SOI substrate structure. The transistor includes a cylinder-type gate insulation layer surrounding the channel region and a gate electrode surrounding the gate insulation layer, having increased integration. This process and structure avoid the characteristic degradation caused by the leakage current associated with the trench process and structure.

Single-transistor logic and CMOS inverters

Abstract: A dual transistor CMOS inverter can be built wherein a single gate is shared by two MOS transistors but only one transistor can be turned on at a time. A CMOS inverter function is provided. Further, a dual transistor logic function is described incorporating a combination of a lateral bipolar transistor (LBT) and a metal-oxide-semiconductor transistor (MOST). The gate of the MOST is used to turn on and off the base of the LBT. When the base is turned on, the LBT is turned on and off depending on the base voltage. This device has, thus, two inputs and can perform logic functions such as OR or NAND, which would typically require four transistors. The invention solves the problem of device density to perform logic by forming stacked devices with shared electrodes.

Non-volatile semiconductor memory device capable of high speed programming/erasure

Abstract: To a column line to which a selected memory cell is connected, a write bias voltage is supplied through a selection gate transistor having different channel conductivity type than the memory cell transistor. Current drivability of the selection gate transistor is adapted to be larger than a leak current of the memory cell and to supply a current smaller than the channel current when a channel is formed in one aspect. When a verifying voltage is applied to the selected word line, a large channel current flows when a channel is formed, potential of a subbit line is changed accordingly, and programming is suppressed. In another aspect, the selection gate transistor serves as a constant current source to make the programming speed of the memory cells constant. Thus distribution of threshold values after programming can be made narrow.

MOS-type solid state imaging device with high sensitivity

Abstract: A solid state imaging device comprises a plurality of unit cells formed in a surface region of a semiconductor substrate. Each of the unit cells comprises a photoelectric converter, an MOS-type read-out transistor for reading a signal from the photoelectric converter, an MOS-type amplifying transistor having a gate connected to a drain of the read-out transistor and for amplifying the signal read by the read-out transistor, a reset transistor having a source connected to the drain of the read-out transistor and for resetting a potential of a gate of the amplifying transistor, and an addressing element connected in series to the amplifying transistor and for selecting the unit cell. The read-out transistor is formed in a first device region in the semiconductor substrate. The reset transistor is formed in a second device region in the semiconductor substrate. The drain of the read-out transistor is connected to the source of the reset transistor through a wiring layer formed on the surface of the semiconductor substrate.

High frequency variable gain amplifier device and wireless communications terminal

Abstract: To obtain a more stable gain control range and to reduce power consumption with a smaller scale circuitry having simpler configuration for gain control, a high frequency variable gain amplifier includes multi stage transistor amplifiers, a change-over switch circuit for controlling supplying and interruption of a power supply voltage, and a field effect transistor switch circuit with grounded-gate connection inserted in a bypass path midway across an input terminal and an output terminal. The source of this field effect transistor switch is in direct current-connection to the drain of a field effect transistor of the final stage transistor amplifier circuit. When a power supply voltage is supplied to each of the transistor amplifiers via the change-over switch circuit, the field effect transistor switch is turned "off" and when the power supply voltage is interrupted, the field effect transistor switch is tuned "on".

Common source transistor capacitor stack

Abstract: New arrangement of a vertical field effect transistor and a capacitor together forming a memory cell which in turn may be the basic building block of a memory chip, such as a very high density DRAM. The capacitor's first electrode is connected to the drain of the transistor. The transistor's source is connected to the sources of other transistors, the gate is connected to a word line, and the second electrode of said capacitor is connected to a bit line.

Integrated voltage regulator circuit with vertical transistor

Abstract: A voltage regulator (10) comprising a vertical channel transistor (12). The vertical channel transistor (12) may have a gate (16), a voltage input terminal (18), and a voltage output terminal (20). A reference voltage supply (14) may be coupled to the gate (16).

Power transistor having vertical FETs and method for making same

Abstract: A power transistor having of a plurality of vertical MOSFET devices combined in parallel to achieve high-performance operation and methods of fabricating this device.

Clock feedthrough reduction system for switched current memory cells

Abstract: The current cell includes a first (M2) and second (M1) MOS transistor connected in series between a constant current source (51) and a reference ground. Each of the two MOS transistor has a respective first (59) and second (63) switch coupling its control gate to its drain. The sample phase of a sample and hold operation is broken down into a first and second sample sub-phase, and an input current (Iin) maintained applied to the current cell during both sample sub-phases. During the first sample sub-phase, the second MOS transistor (M1) memorizes a gate voltage corresponding to the input current (Iin), constant current source (51) and a clock feedthrough error. A modulation voltage (Vmod) is induced at the drain (62) of the second transistor (M1) as a result of the channel effect, and the first MOS transistor (M2) is used to store and maintain this modulation voltage (Vmod) at the drain (62) of the second MOS transistor (M1) during the hold phase.

Overcurrent sensing circuit for power MOS field effect transistor

Abstract: An overcurrent sensing circuit for sensing an overcurrent flowing through a power MOS transistor is described. A voltage drop equal to the voltage across the drain and source of a power MOS transistor that changes due to change in a load current is generated in a sensing resistor that is connected between the source of a sensing MOS transistor having its gate and drain connected in common with those of the power MOS transistor and the source of the power MOS transistor due to current that flows through the sensing MOS transistor. This voltage is inputted to a comparator that has an added offset voltage, and the comparator judges that the power MOS transistor is in an overcurrent condition when this inputted voltage exceeds an input offset voltage value that is set inside the comparator.

Ultra high density series-connected transistors formed on separate elevational levels

Abstract: A three-dimensional integrated circuit and fabrication process is provided for producing active and passive devices on various levels of the integrated circuit The present process is particularly suited to interconnecting a source of one transistor to a drain of another to form series-connected transistors often employed in core logic units A junction of an underlying transistor can be connected to a junction of an overlying transistor, with both transistors separated by an interlevel dielectric The lower transistor junction is connected to the upper level transistor junction using a plug conductor The plug conductor and, more specifically, the mutually connected junction, is further coupled to a laterally extended interconnect The interconnect extends from the mutual connection point of the plug conductor to a substrate of the overlying transistor Accordingly, the source and substrate of the overlying transistor can be connected to a drain of the underlying transistor to not only achieve series-connection but also to connect the source and substrate of an internally configured transistor for the purpose of reducing body effects

Load actuation circuit

Abstract: An output MOS transistor (2) and a current-detecting MOS transistor (3) are connected commonly at their drains and gates. A gate voltage is fed to the gates of these transistors via signal lines (L1, L2). When the voltage of an output terminal (10) is increased in response to excessive load current, a current-mirror circuit (100) consisting of first and second transistors (4, 5) pulls in current from the signal line (L2) to reduce the gate voltage. Thus, the output current (I1) of output MOS transistor (2) is limited within a predetermined level. Furthermore, a diode (8), provided in the signal line (L2), produces a voltage drop equivalent to the base-emitter voltage of first transistor (4). By the function of this diode (8), the gate-source voltage of output MOS transistor (2) is equalized with the gate-source voltage of current-detecting MOS transistor (3). As a result, the same operating point can be set for the output transistor (2) and the current-detecting transistor (3).

Bootstrap circuit suitable for buffer circuit or shift register circuit

Abstract: A potential across an output terminal (OUT) is applied to a node N2 through a transistor (Tr66) even when a potential across a node N1 is higher than a power source voltage Vdd due to a bootstrap effect. Accordingly, the potentials between the drain and the source electrodes are not higher than the power source voltage Vdd for both a transistor (Tr62) and the transistor (Tr66). This allows circuit designing without setting the withstand voltage for the transistor over the power source voltage Vdd.

Reduced parasitic resistance and capacitance field effect transistor

Abstract: A field effect transistor and method for making the same is described wherein the field effect transistor incorporates a T-shaped gate and source and drain contacts self-aligned with preexisting shallow junction regions. The present invention provides a low resistance gate electrode and self-aligned low resistance source/drain contacts suitable for submicron FET devices, and scalable to smaller device dimensions.

Salient integration mode active pixel sensor

Abstract: A salient integration mode active pixel sensor. The active pixel sensor includes an amplify/compare transistor which has a threshold voltage. The amplify/compare transistor couples an input of the amplify/compare transistor to an output of the amplify/compare transistor when the input of the amplify/compare transistor exceeds the threshold voltage. A photo-diode generates a signal voltage which has a voltage level dependent upon the intensity of light received by the photo-diode. The signal voltage is coupled to the input of the amplify/compare transistor. A reset element couples a reset line to the photo-diode and discharges the photo-diode when the reset line is active. A coupling capacitor for couples a select line to the input of the amplify/compare transistor. The select line causes the input to the amplify/compare transistor to exceed the threshold voltage and thereby couple the signal voltage to the output of the amplify/compare transistor. The amplify/compare transistor can be an N-type MOSFET and the reset transistor can be an N-type MOSFET. Further, a back gate of the amplify/compare transistor is generally connected to a circuit ground.

Avalanche-enhanced CMOS transistor for EPROM/EEPROM and ESD-protection structures

Abstract: A non-volatile memory cell uses a p+ diffusion region spaced a lateral distance from the n+ drain of the n-channel programmable transistor. A diode between this p+ diffusion and the n+ drain has a low breakdown voltage because of the close spacing of the high-doping n+ and p+ diffusions. This diode generates electrons when avalanche breakdown occurs. The avalanche electrons are swept up into the programmable gate during programming. Since the avalanche electrons are generated by the diode rather than by the programmable transistor itself, programming efficiency no longer depends on the channel length and other parameters of the programmable transistor. The breakdown voltage of the diode is adjusted by varying the lateral spacing between the n+ drain and the p+ diffusion. Smaller lateral spacing enter avalanche breakdown at lower voltages and thus program the programmable transistor at a lower drain voltage. A drain voltage less than the power supply is possible with the diode, eliminating the need for a charge pump for the drain. A deep p-type implant under the n+ drain can also form the diode. The diode can be used for input-protection (ESD) devices.

Memory circuit including write control unit wherein subthreshold leakage may be reduced

Abstract: A memory circuit wherein subthreshold leakage current may be reduced. The memory circuit includes a memory array composed of one or more storage cells that are each configured to store a memory value on a storage transistor. The storage cells further include a write transistor coupled to the storage transistor that is configured to allow data driven on a write bit line to be stored to the storage transistor. The write bit line is coupled to a write control unit, which includes a buffer and a offset voltage element. The buffer is configured to establish an output voltage on the write bit line in response to an input voltage. The offset voltage element is coupled to the buffer, and is configured to offset the output voltage on the write bit line by a predetermined amount. In one implementation of the write control unit, the buffer is formed by an inverter that includes a p-channel and an n-channel transistor. The offset voltage element is a diode-connected transistor coupled between the inverter and ground. The diode-connected transistor has the effect of holding the write bit line at a level equal to its threshold voltage when the n-channel transistor of the inverter is active. In another implementation, the buffer is also an inverter that includes a p-channel and an n-channel transistor. The offset voltage element is a pullup transistor that is active when the n-channel transitor of the inverter is active. The pullup transistor forms a voltage divider with the n-channel transistor, such that the voltage between the write bit line and ground is offset by an amount determined by the voltage drop across the pullup transistor. The offset voltage established by the write control unit biases the write transistor such that subthreshold leakage current may be reduced when the write transistor is off.

Solid-state antenna switch and field-effect transistor

Abstract: A field-effect transistor has a covering electrode overlying at least part of the transistor's channel. The covering electrode is formed on an insulating layer that covers the source, gate, and drain of the transistor. One voltage is applied to the covering electrode when the field-effect transistor is switched on. Another voltage is applied when the field-effect transistor is switched off, creating an electric field that hinders current flow in the channel. In an antenna switch, this type of transistor couples an antenna to a receiving circuit, and another transistor couples the antenna to a transmitting circuit.

High-performance InGaP/InGaAs/GaAs step-compositioned doped-channel field-effect transistor (SCDCFET)

Abstract: A new i-In0.49Ga0.51P/n-InxGa1-xAs/i-GaAs step-compositioned doped-channel field-effect transistor (SCDCFET) has been fabricated and studied. Owing to the presence of a V-shaped energy band formed by the step-compositioned doped-channel structure, a large current density, a large gate voltage swing with high average transconductance and a high breakdown voltage are obtained. For a 1 × 80 µm2 gate dimension, a maximum drain saturation current of 830 mA/mm, a maximum transconductance of 188 mS/mm, a high gate breakdown voltage of 34 V, and a large gate voltage swing of 3.3 V with transconductance > 150 mS/mm are achieved. These performances show that the studied device has a good potentiality for high-speed, high-power, and large input signal circuit applications.

Switch-mode power supply with over-current protection

Abstract: In a tuned switch mode power supply a zero voltage is maintained across a transistor switch (Q3), during both turn off and turn on switching transition intervals in the transistor switch. The tuned switch mode power supply operates in a current-mode control, on a current pulse-by-current pulse control basis. An over-current protection circuit (200) disables the transistor switch when an over-current condition persists longer than a first interval that is substantially longer than a period of a given current pulse in the transistor switch. The operation of the transistor switch is undisturbed, when the over-current condition lasts only a shorter interval than the first interval.