Showing papers on "Static induction transistor published in 1999"

Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering

Abstract: A method of modifying the mobility of a transistor. First, a transistor having a gate is formed. A substance is then implanted in the gate. The transistor is annealed such that the implanted substance forms at least one void in the transistor's gate.

Current-efficient low-drop-out voltage regulator with improved load regulation and frequency response

Abstract: A low drop-out (LDO) voltage regulator ( 10 ) and system ( 100 ) including the same are disclosed. An error amplifier ( 38 ) controls the gate voltage of a source follower transistor ( 24 ) in response to the difference between a feedback voltage (V FB ) from the output (V OUT ) and a reference voltage (V REF ). The source of the source follower transistor ( 24 ) is connected to the gates of an output transistor ( 12 ), which drives the output (V OUT ) from the input voltage (V IN ) in response to the source follower transistor ( 24 ). A current mirror transistor ( 14 ) has its gate also connected to the gate of the output transistor ( 12 ), and mirrors the output current at a much reduced ratio. The mirror current is conducted through network of transistors ( 18, 22 ), and controls the conduction of a first feedback transistor ( 28 ) and a second feedback transistor ( 35 ) which are each connected to the source of the source follower transistor ( 24 ) and in parallel with a weak current source ( 34 ). The response of the first feedback transistor ( 28 ) is slowed by a resistor ( 32 ) and capacitor ( 30 ), while the second feedback transistor ( 35 ) is not delayed. As such, the second feedback transistor ( 35 ) assists transient response, particularly in discharging the gate capacitance of the output transistor ( 12 ), while the first feedback transistor ( 28 ) partially cancels load regulation effects.

Methods for designing standard cell transistor structures

Abstract: Disclosed are methods for designing standard cell transistor layouts for minimizing transistor delays and for minimizing power consumption. The method of minimizing transistor delays includes defining a transistor model for a P-type transistor and an N-type transistor of a CMOS standard cell. The method then includes minimizing a ratio between the P-type transistor and the N-type transistor. The ratio is defined by dividing a P-type gate width of the P-type transistor by an N-type gate width of the N-type transistor. The optimizing is performed by substantially minimizing an average delay for the transistor structure. In this embodiment, the CMOS standard cell will define a transistor structure that is implemented to make a logic circuit. The CMOS standard cell is one of a library of standard cells, where each standard cell defines a particular logic circuit.

Thin-film transistor circuitry with reduced sensitivity to variance in transistor threshold voltage

Abstract: A circuit design technique polysilicon thin-film transistor (TFT) circuitry produces circuits that are relatively less sensitive to threshold variations among the TFT's than circuits designed using conventional techniques. The circuit is designed such that thin-film transistors that are sensitive to threshold variations are made larger than other thin-film transistors in the circuitry to minimize threshold variations among similar transistors implemented in the circuit. In one embodiment, a pixel structure for an active matrix display device implemented in polysilicon includes two transistors, a select transistor and a drive transistor. The drive transistor in the pixel structure is a thin film metal oxide silicon (MOS) transistor that includes a gate to source capacitance sufficient to hold an electrical potential which keeps the transistor in a conducting state for an image field interval. One embodiment of the pixel structure includes only the select transistor and the drive transistor. The pixel storage capacitance is entirely realized by the gate to source capacitance of the drive transistor. Another embodiment of the pixel structure includes a capacitor which is much smaller than the capacitor of a conventional active matrix pixel structure. This capacitor holds the pixel in a non-illuminated state when the drive transistor is turned off. This pixel structure may be used with any display technology that uses an active matrix and stores image data on a capacitance in the pixel, including without limitation, organic light emitting diodes, electroluminescent devices, and inorganic light emitting diodes.

Transistor circuit, display panel and electronic apparatus

Abstract: A transistor circuit is provided including a driving transistor where conductance between the source and the drain is controlled in response to a supplied voltage, and a compensating transistor where the gate is connected to one of the source and the drain, the compensating transistor being connected so as to supply input signals to the gate of the driving transistor through the source and drain. In a transistor circuit where conductance control in a driving transistor is carried out in response to the voltage of input signals, it is possible to control the conductance by using input signals of a relatively low voltage and a variance in threshold characteristics of driving transistors is compensated. With this transistor circuit, a display panel that can display picture images with reduced uneven brightness is achieved.

High power high impedance microwave devices for power applications

Abstract: Simplified, efficient multiple-transistor power amplifiers provide high power and high impedance while avoiding the use of RF power divider and combiner circuits. The input signal is directly applied to a first transistor, amplified, and supplied to the succeeding transistor, and so on, for amplification in series. Feedback is provided between the drain of the last transistor and the gates of all the transistors. Series connection of the transistors allows their power outputs and their output impedances to be summed, such that no RF output combiner is required. In a first high voltage embodiment of the amplifier of the invention, e.g., as used for satellite transmission, bias voltage is provided in series. In a second low voltage embodiment, suitable for use in cordless telephones and other battery-powered equipment, bias voltage Vds is provided separately across the drain and source terminals of each transistor, through paired chokes.

Circuit driver on SOI for merged logic and memory circuits

Abstract: A silicon-on-insulator digital circuit combination having a body voltage control stage and a voltage clamp stage. The body voltage control stage is responsive to an input control signal to provide an output driver signal. The body voltage control stage has a first transistor with a terminal for electrically-coupling to a combinational logic circuit, and a body contact electrically-coupled to the input control signal such that a threshold voltage of the transistor is reduced when the transistor is placed in an active state. It can be readily appreciated that the reduced threshold voltage of the transistor increases the transition rate for the first transistor to an inactive state in response to the input control signal. The voltage clamp stage has a second transistor responsive to the input control signal such that the terminal is electrically-coupled to a reference voltage when the first transistor is in the inactive state.

Implementation of EEPROM using intermediate gate voltage to avoid disturb conditions

Abstract: A method and apparatus for erasing a single floating gate transistor in an array of floating gate transistors is provided. A selected floating gate transistor, which is located in a first row and a first column of the array, is erased as follows. A low voltage VLOW (e.g., 0 Volts) is applied to the gate of each transistor in the first row of the array. An erase voltage VERASE (e.g., 8 Volts) is applied to the drain of each transistor in the first column of the array. An intermediate voltage VINT (e.g., 3 Volts) is applied to the source of each transistor in the array, as well as to the drain of each transistor of the array that is not in the first column. Under these conditions, only the selected floating gate transistor is erased. Other floating gate transistors in the first column are not erased because the gate-to-drain voltages of these transistors are limited by the intermediate voltage VINT applied to their gates.

Power circuit including inrush current limiter, and integrated circuit including the power circuit

Abstract: A power circuit including means for preventing the generation of an inrush current during the power circuit's initial operation without increasing the size of the power circuit is described. The power circuit comprises an output transistor for supplying a current from a power supply to an output terminal, and a differential amplifier for controlling the current supplied by the output transistor in such a manner as to regulate a voltage at the output terminal based on a preset reference voltage. A limiting transistor is provided as a source follower on a current path at the output stage of the differential amplifier. The gate potential of the output transistor is controlled using the source potential of the limiting transistor. Before the power circuit starts to operate, an operation controller charges a capacitor to control the gate potential of the limiting transistor so that during the initial operation of the power circuit, the capacitor is discharged by using a current source. Accordingly, during the initial operation of the power circuit, the gate potential of the limiting transistor gradually decreases while the gate-source voltage of the output transistor gradually increases. As a result, the generation of the inrush current can be suppressed.

Semiconductor integrated circuit and method for manufacturing the same

Abstract: A semiconductor integrated circuit according to the present invention comprises a MOS transistor formed on an SOI substrate and a subsidiary transistor provided between a body node and a drain node of the MOS transistor and sharing a gate electrode with the MOS transistor, whereby body potential of the MOS transistor is controlled by gate and drain potentials. Accumulated body charge in a non-conducting state in the semiconductor integrated circuit is extracted by a resistor formed between the body node and a source, whereby various phenomena caused by floating body effect are eliminated. Since the body potential of the MOS transistor can be varied without creating an undesirable leakage current path, and hence without limitations to supplied voltage, its threshold voltage can be made variable so as to follow change in an input signal, thereby making it possible to achieve higher speed and lower voltage operation of the semiconductor integrated circuit. According to the present invention, it is possible to eliminate floating body effect, which is the greatest problem with an SOI transistor formed on an SOI substrate, and also to achieve lower voltage and greater current operation of a transistor without posing limitations to supplied voltage and without causing the problem of leakage current.

Influence of soft breakdown on NMOSFET device characteristics

Abstract: The degradation of important transistor parameters related to soft breakdown and hard breakdown were studied. Long and short channel transistors were homogeneously stressed at elevated temperature until soft breakdown or hard breakdown occurred. The only noticeable signature of soft breakdown is an increase in off current due to enhanced gate induced drain leakage current. This effect arises if the soft breakdown is located within the gate-to-drain overlap region. Soft breakdown generates a spot or path of negative charges in the oxide and therefore enhances gate induced drain leakage current.

Device Characteristics of Organic Static Induction Transistor Using Copper Phthalocyanine Films and Al Gate Electrode

Abstract: We have fabricated organic static induction transistors (SITs) using copper phthalocyanine (CuPc) films. The organic SITs have a layered structure of Au (drain)/CuPc/Al (gate)/CuPc/Au (source)/glass. The electrical characteristics of SITs show that the source-drain current is controlled by the bias voltage applied to the Al gate electrode and a typical SIT operation with unsaturated current characteristics is examined. Furthermore, excellent characteristics such as low voltage and high speed operation as organic transistors are obtained by choosing an appropriate thickness for each layer.

Charge sensitivity of radio frequency single-electron transistor

Abstract: A theoretical analysis of the charge sensitivity of the radio frequency single-electron transistor (rf-SET) is presented. We use the “orthodox” approach and consider the case when the carrier frequency is much less than I/e where I is the typical current through rf-SET. The optimized noise-limited sensitivity is determined by the temperature T, and at low T it is only 1.4 times worse than the sensitivity of conventional single-electron transistor.

Voltage controlled oscillator utilizing threshold voltage control of silicon on insulator MOSFETS

Abstract: A voltage controlled ring oscillator (VCRO) that can operate at low voltage and provide a variable periodic output. A plurality of transistors form a ring oscillator and a selected transistor in the ring oscillator has a body which can float with respect to ground potential. The selected transistor has a threshold voltage which is controllable by a voltage applied to the transistor body. A control input is coupled to the transistor body such that the body of the transistor can be charged by the control input. Charging the body alters the threshold voltage of the transistor and thereby controls the oscillation frequency of the oscillator.

SOI transistor with body contact and method of forming same

Abstract: An SOI field effect transistor is provided comprising a body contact that is isolated by a shallow trench that is formed into the body portion of the transistor, thereby eliminating any increase in gate capacitance or delay. A method of forming such a transistor is provided that does not require any additional process steps.

Radio frequency amplifiers

Abstract: A radio frequency amplifier having a power transistor (Q1) to the base of which is coupled a radio frequency signal to be amplified. An amplified radio frequency signal is provided at the collector of the power transistor (Q1). A control transistor (Qc) has its base coupled to the base of the power transistor (Q1) while a driver transistor (Q2) provides a control bias signal to the bases of the control and power transistors. A differential amplifier (Qd1, Qd2) has a first input coupled to an input bias signal and an output coupled to the base of the driver transistor (Q2). The collector of the control transistor (Qc) is coupled to a second input of the differential amplifier to provide a negative feedback signal to the differential amplifier and the driver transistor (Q2) and thereby to stabilise the operating point of the power transistor (Q1).

Semiconductor device with DMOS, BJT and CMOS structures

Abstract: A semiconductor device having a substrate composed of a DMOS transistor, a complementary MOS (CMOS) transistor and a bipolar junction transistor is disclosed. A highly-doped bottom layer is formed on a lower edge of a body region of the DMOS transistor, a heavily doped bottom layer of a conductivity type opposite to that of the substrate is formed on a lower edge of source and drain regions of the CMOS transistor, and a highly-doped bottom layer of the same conductivity type as that of the substrate is formed on a lower portion of an intrinsic base region of the bipolar junction transistor, to thereby enhance the electrical characteristics of devices.

A memory cell with single-electron and metal-oxide-semiconductor transistor integration

Abstract: A single-electron transistor memory cell with metal-oxide-semiconductor field-effect transistor sensing has been fabricated in silicon-on-insulator material. The single-electron transistor, coupled to a memory node, is defined in the upper silicon layer. The memory node forms the gate of a metal-oxide-semiconductor field-effect transistor with its channel in the substrate silicon. At 4.2 K, there are two different states of the memory-node voltage, separated by the single-electron transistor Coulomb gap. These states are sensed at high-current output levels by the metal-oxide-semiconductor transistor. The metal-oxide-semiconductor transistor current also shows evidence of gate-dependent conductance oscillations in the coupled single-electron transistor.

Method and apparatus for producing a single polysilicon flash EEPROM having a select transistor and a floating gate transistor

Abstract: Accordingly, exemplary embodiments of the present invention are directed to single poly flash EEPROM cells which avoid the drawbacks of conventional two poly stacked gate cells, and which are easily integrated with high performance logic technologies. An exemplary two transistor flash-EEPROM memory cell array comprises a plurality of these flash EEPROM cells, each having a select transistor with a bit line and a word line, where the select transistor is in series with a floating gate transistor. The floating gate transistor has a thin tunneling oxide formed on a textured monocrystalline substrate. The floating gate is also formed over a heavily doped region in the substrate which forms a coupling line capacitively coupled to the floating gate, and which performs a tunneling function.

Low power SOI ESD buffer driver networks having dynamic threshold MOSFETS

Abstract: A method and structure for a body coupled driver circuit includes a pull-up stage having a first transistor and a pull-down stage having a second transistor. The first transistor and the second transistor have bodies coupled to either a reference voltage or a pad node.

Match line control circuit for content addressable memory

Abstract: A match line control circuit includes a weak, static pull-up transistor and a strong, dynamic pull-up transistor coupled between a match line of an associated CAM and a supply voltage. Prior to compare operations, both the static pull-up transistor and the dynamic pull-up transistor are in a conductive state and thereby quickly charge the match line to the supply voltage. During compare operations, the dynamic transistor is turned off to reduce current flow between the supply voltage and the match line. In some embodiments, the static pull-up transistor and the dynamic pull-up transistor are configured to match the parasitics of the CAM cells 10 coupled to the match line, thereby increasing performance of the associated CAM.

Semiconductor integrated circuit device including electrostatic protection circuit accommodating drive by plurality of power supplies and effectively removing various types of surge

Abstract: According to a structure in which each transistor of an output buffer transistor group of a gate array structure is electrically isolated, each body potential is set independent Also, a diode-connected transistor is provided between power supplies. An element not used in the output buffer transistor group can be connected without short-circuiting power supply lines between independent power supply lines to form an electrostatic protection circuit that is efficient in layout.

Soi voltage-tolerant body-coupled pass transistor

Abstract: A method and device for A pass transistor device which includes a source; a drain opposite the source, a body between the source and the drain, and a circuit control network connected between the drain and the source, wherein the circuit control network controls a potential voltage of the body and provides overvoltage protection to the pass transistor.

Transistor with dynamic source/drain extensions

Abstract: A method of fabricating an integrated circuit with a transistor having less susceptibility to off-state leakage current and short-channel effect is disclosed. The transistor includes high-K gate dielectric spacers and a T-shaped gate conductor. The high-K dielectric spacers can be tantalum pentaoxide or titanium dioxide. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETs). The T-shaped conductor forms dynamic source/drain extensions.

Non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS process

Abstract: A non-volatile memory cell is provided that includes a low voltage CMOS storage transistor having a source region and a drain region that are commonly connected to ground. The low voltage storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. The high programming voltage is applied to the low voltage storage transistor through a high voltage p-channel transistor. The high voltage p-channel transistor has a thicker gate oxide than the storage transistor, thereby enabling the p-channel transistor to withstand higher voltages. The high voltage p-channel transistor also has a higher breakdown voltage than a high voltage n-channel transistor of the same size. Both the low voltage storage transistor and the high voltage p-channel transistor are fabricated in accordance with a standard sub 0.35 micron process. The state of the low voltage storage transistor can be read through the p-channel transistor, or through a dedicated high voltage n-channel transistor. In one embodiment, the programming voltage is generated by a charge pump circuit fabricated in accordance with a standard sub 0.35 micron process. In another embodiment, the decoder circuits that access the non-volatile memory cell use high voltage p-channel transistors to transmit the high programming voltage. Another embodiment of the present invention includes a system-on-a-chip structure that implements the non-volatile memory of the present invention.

Direct-current stabilization power supply device

Abstract: A current detection resistance such as a metal resistance is formed in series with a power transistor, and in response to an output voltage of the current detection resistance, an overcurrent protective circuit performs an overcurrent suppressing operation with high accuracy without being affected by irregularity of a current multiplication factor, etc.; thus, it is possible to realize a smaller chip area so as to reduce the cost. Furthermore, a short-circuit protective circuit returns a terminal voltage of a referenced resistance, that appears in accordance with a partial pressure value of an output voltage, at the transistor, a partial pressure resistance, and a current mirror circuit. And the short-circuit protective circuit controls a potential of a base resistance and suppresses a base current. Hence, it is not necessary to dispose the transistor for suppressing a current between base lines, so that a low-voltage operation can be realized. In a direct-current stabilization power supply device having a two-chip structure of a PNP power transistor and a control IC, it is possible to achieve a smaller chip area and a low-voltage operation.

VDMOS transistor protected against over-voltages between source and gate

Abstract: The n-channel VDMOS transistor is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed in the same active region and has its gate electrode connected to the gate electrode of the VDMOS transistor, its source region in common with the source region of the VDMOS transistor, and its drain region connected to the p-type junction-isolation region. The p-channel MOS transistor has a threshold voltage below the breakdown voltage of the gate dielectric of the VDMOS transistor so that it acts as a voltage limiter.

Mobile ionic contamination detection in manufacture of semiconductor devices

Abstract: A test transistor structure formed in a semiconductor device has a thick-oxide transistor with an elongated serpentine-shaped metal gate. The gate is used to first measure the threshold voltage of the thick-oxide test structure. Then, a current is passed through the elongated metal line which forms the serpentine gate to heat the area of the test structure. While being heated, a stress voltage is applied between the substrate and one end of the gate electrode, this stress voltage being much larger than the logic voltage used in operating thin-oxide transistors on the chip. After a selected time, the current is removed, the stress voltage is removed, and the threshold voltage of the thick-oxide transistor is again measured and compared to the original value. Any reduction in threshold voltage can be attributed to the migration of positive charge to the silicon-to-oxide interface beneath the gate, and is proportional to the area between the source and drain regions of the test transistor.

Voltage blocking method and apparatus for a charge pump with diode connected pull-up and pull-down on boot nodes

Abstract: A negative charge pump circuit is disclosed. The pump circuit includes several stages, each stage including a switching transistor, a pull up diode, and a pull down diode. The pump circuit also includes a blocking transistor coupled between the gate terminal of the switching transistor and the pull down diode of the third stage. The gate terminal of the blocking transistor is electrically coupled to the source terminal of the switching transistor of the first stage where the first stage provides the output for the negative charge pump circuit. A voltage present at the output of the first stage is delivered to the gate terminal of the switching transistor of the third stage when a positive programming voltage is present at the output of the first stage in order to block the positive programming voltage from shorting to ground through the negative pump circuit. The blocking transistor prevents the voltage applied to the gate of the switching transistor of the third stage from flowing through the pull-down diode of the third stage.

Single charge carrier transistor, method of holding a charge carrier within a quantum dot, and method of detection

Abstract: A single electron on hole field effect transistor fabricated from a narrow band gap semiconductor. The transistor is such that the valence and conduction bands have sufficiently similar energy levels such that a top region of the valence band at one point (37), e.g. under a gate electrode (34), within the current path of the transistor can be forced to be higher than the bottom region of the conduction band at another point within the transistor, allowing Zener tunnelling to occur. The transistor is fabricated from semiconductors with band gaps narrow enough to allow this to occur, for instance InSb and InAISb, CdTe and CdxHg1-xTe.