Showing papers on "Static induction transistor published in 2001"

Current-reuse bleeding mixer

Abstract: A current-reusing bleeding mixer capable of providing a higher conversion gain, linearity and lower noise figure employing a field-effect transistor includes a first to a fourth transistor and a first and a second load element. The first transistor amplifies a radio frequency (RF) signal. The second and the third transistor, each connected to the first transistor, receive a balanced local oscillator (LO) signal to mix it with the RF signal. The first and the second load element are connected between a supply voltage source and the second transistor and between the supply voltage source and the third transistor, respectively. The fourth transistor, connected between the supply voltage source and the first transistor, amplifies the RF signal and bleeds a current from the supply voltage source.

Influence of impact-ionization-induced instabilities on the maximum usable output voltage of Si-bipolar transistors

Abstract: The onset of impact-ionization-induced instabilities limits the operating range of Si-bipolar transistors, especially in power stages. Therefore, analytical relations which characterize the onset of instabilities are derived for different driving conditions (mainly V/sub BE/=const. and I/sub E/=const.) and arbitrary transistor geometries. They allow the designer and technologist to calculate the maximum usable dc output voltage in dependence on transistor dimensions and technological parameters. As a consequence, the voltage range above BV/sub CE0/ can now be more intensively and reliably used and thus the performance potential of a given technology can be better exploited. However, the reduction of the maximum tolerable output voltage with increasing emitter (or collector) current must be carefully considered. The presented theory and analytical results are verified by three-dimensional (3-D) transistor simulations and by measurements.

High sensitivity common source amplifier MRAM cell, memory array and read/write scheme

Abstract: In the present invention, a magnetic random access memory (MRAM) cell includes a magnetic tunnel junction (MTJ) and a transistor This memory cell provides a boosted output signal between different MTJ states stored A method that is used by MRAM array for providing larger output voltage signal is also disclosed The memory may comprise a plurality of such cells which are wired to form XY array The source of the transistor is coupled to one end of the magnetic tunneling junction, while the drain of the transistor is coupled with an output for reading the magnetic memory cell Another end of the magnetic tunneling junction is grounded During reading, a constant voltage is applied to the gate of the transistor in selected memory cell The drain of the transistor is connected to supply voltage via a load The transistor functions both as switching element and amplifier to boost the output signal between different MTJ states Either voltage or current at output can be detected to determine MTJ state

Display device having current-addressed pixels

Abstract: A display device has current-addressed pixels, with the currents being supplied by driver circuitry which comprises a transistor (10) for applying a charging voltage to a switched capacitor arrangement (Ci, S1, S2) arranged to selectively charge and discharge the capacitor (Ci) at a predetermined rate to a charging voltage. A transistor control voltage (Vref) is applied to a control terminal of the transistor which is adjusted depending on the transistor threshold voltage to ensure that the capacitor (Ci) is charged to the charging voltage irrespectively of the value of the threshold voltage. This enables an accurately controllable current to be provided which is used to drive the current-addressed pixels.

Driving method for electro-optical device, electro-optical device, and electronic apparatus

Abstract: The invention provides a method for implementing a multi-level display of an electro-optical device according to a time ratio gray-scale method without providing reset lines. In an electro-optical device that includes, at an intersection of a scanning line and a data line, an electro-optical element, a driving transistor that drives the electro-optical element, and a switching transistor that controls the driving transistor, a gray-scale is obtained by performing a plurality of set-reset operations. Each set-reset operation includes: a setting step of supplying an on-signal to the switching transistor via the scanning line, and of supplying a set signal to select a conducting state or a non-conducting state of the driving transistor to the driving transistor via the data line and the switching transistor in accordance with the one signal; and a resetting step of supplying an on-signal to the switching transistor via the scanning line, and of supplying a reset signal to select the non-conducting state of the driving transistor to the driving transistor via the data line and the switching transistor in accordance with the one signal.

Constant current driver with auto-clamped pre-charge function

Abstract: A constant current driver with auto-clamped pre-charge function includes a reference bias generator and a plurality of constant current driver cells, each being connected to the reference bias generator to form a respective current mirror. Each constant current driver cell has a switch transistor, a current output transistor and a pre-charge transistor. When a constant current is outputted from the current output transistor for driving an organic light emitting diode, the pre-charge transistor is turned on to provide a drain to source current as an additional large current for rapidly pre-charging the organic light emitting diode until the gate to source voltage of the pre-charge transistor is smaller than the threshold voltage.

Active driving circuit for display panel

Abstract: An active driving circuit for a display panel includes first to fourth transistors, a capacitor, a constant current source, and a capacitor. The first transistor is connected with a positive power source. The second transistor has a common gate terminal together with the first transistor and a mirror circuit against the first transistor. Also, the second transistor is turned on by a common gate signal applied to the common gate terminal to supply the positive power source to a display device. The third transistor sets a saturated threshold voltage for the common gate terminal by allowing the first transistor and the second transistor to constitute a mirror circuit against each other in accordance with a scan line signal. The constant current source supplies a current with a ground one side and controlled by a gray signal of a data line. The fourth transistor sets the common gate voltage corresponding to the controlled current of the constant current source by the scan line signal. The capacitor accumulates charges corresponding to the difference between the positive power source and the common gate voltage.

Radio-frequency single-electron transistor: Toward the shot-noise limit

Abstract: We have fabricated an aluminum single-electron transistor and characterized it at frequencies up to 10 MHz by measuring the reflected signal from a resonant tank in which the transistor is embedded. We measured the charge sensitivity of this radio-frequency single-electron transistor to be 3.2×10−6 e/Hz, which corresponds to the uncoupled energy sensitivity of 4.8 ℏ. Our measurements indicate that with further improvements, the radio-frequency single-electron transistor could reach the shot-noise limit estimated to be about 1 ℏ.

Semiconductor memory device with floating storage bulk region and method of manufacturing the same

Abstract: A memory cell MC comprises one MOS transistor having a floating bulk region which is electrically isolated from others. A gate electrode 13 of the MOS transistor is connected to a word line WL, a drain diffusion region 14 thereof is connected to a bit line BL, and a source diffusion region 15 thereof is connected to a fixed potential line SL. The memory cell stores a first threshold state in which majority carriers produced by impact ionization are injected and held in the bulk region 12 of the MOS transistor and a second threshold state in which the majority carriers in the bulk region 12 of the MOS transistor are emitted by a forward bias at a pn junction on the drain side as binary data. Thereby, a semiconductor memory device in which a simple transistor structure is used as a memory cell, enabling dynamic storage of binary data by a small number of signal lines can be provided.

Method for forming asymmetric dual gate transistor

Abstract: The present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping one of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. Additionally, the preferred transistor design uses an asymmetric structure that results in reduced gate-to-drain and gate-to-source capacitance. In particular, dimensions of the weak gate, the gate that has a workfunction less attractive to the channel carriers, are reduced such that the weak gate does not overlap the source/drain regions of the transistor. In contrast the strong gate, the gate having a workfunction that causes the inversion layer to form adjacent to it, is formed to slightly overlap the source/drain regions. This asymmetric structure allows for the performance benefits of a double gate design without the increased capacitance that would normally result.

Technique to mitigate short channel effects with vertical gate transistor with different gate materials

Abstract: This invention relates to a process of forming a transistor with three vertical gate electrodes and the resulting transistor. By forming such a transistor it is possible to maintain an acceptable aspect ratio as MOSFET structures are scaled down to sub-micron sizes. The transistor gate electrodes can be formed of different materials so that the workfunctions of the three electrodes can be tailored. The three electrodes are positioned over a single channel and operate as a single gate having outer and inner gate regions.

Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device

Abstract: A memory device is described which has an n-channel field effect transistor coupled between a memory cell and a data communication line. An NPN bipolar junction transistor is also coupled between the memory cell and the data communication line in parallel to the n-channel access transistor. A base connection of the NPN bipolar junction transistor is described as coupled to a body of the n-channel access transistor. During operation the n-channel field effect transistor is used for writing data to a memory cell, while the NPN bipolar junction transistor is used for read operations in conjunction with a current sense amplifier circuit. The access transistors are described as fabricated as a single vertical pillar.

A new NMOS layout structure for radiation tolerance

Abstract: A new transistor structure is presented to obtain radiation tolerance in commercial submicron CMOS technology without any process modifications. The NMOS transistor and field leakage normally induced by ionizing irradiation is remedied by acting on the work function of the transistor gate at the transistor edges. The technique also works in a CMOS process where transistor source and drains are silicided. Contrary to the enclosed layout transistor (ELT) previously proposed for this purpose, this new transistor structure does not limit the transistor width over transistor length (W/L) ratios to large values and thereby eliminates one of the most stringent constraints in the design of radiation tolerant circuits in standard CMOS. Measurements on fabricated devices demonstrate the functionality of the transistor structure and its radiation tolerance up to 40 Mrad(SiO/sub 2/).

CMOS transceiver having an integrated power amplifier

Abstract: The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator. This results in the first transconductance being greater than the second transconductance, and the second breakdown voltage being greater than the first breakdown voltage.

Two-dimensional simulation of polymer field-effect transistor

Abstract: A two-dimensional simulation of intrinsic top-contact field-effect transistor is presented. The simulated structure is unique to organic transistors and hence is most relevant. By time resolving the operation of such a transistor, the mechanisms underlying its operation are resolved. The effect of this device configuration on the measured “intrinsic” material properties is also discussed and shown to explain previously reported features.

Dual drive buck regulator

Abstract: A switching regulator of the step down variety is disclosed. First and second transistors coupled in parallel between a first supply node and a first output node are controlled by a driver stage to sequentially (1) switch on the first transistor, (2) switch on the second transistor, (3) switch off the second transistor, and (4) switch off the first transistor. The first transistor is smaller than the second transistor, such that the first transistor can switch faster than the second transistor, thereby reducing power dissipation during the time intervals in which both transistors are switching. Such a design allows an increase in switching frequency without the conventional increase in power dissipation, in return for a relatively inexpensive change of adding an additional, smaller transistor in parallel with a larger one, and associated circuitry in the driver stage.

Organic polarizable gate transistor apparatus and method

Abstract: An apparatus having a circuit coupled to the gate contact of field effect transistor wherein the transistor's gate includes a dielectric layer of which at least a portion is an organic dielectric. The circuit is configured to produce one or more storage voltage pulses that cause charge to be stored in the dielectric layer. The field effect transistor has a semiconductor layer with a conductive path whose conductivity changes for a given V g in response to storing the charge. The circuit may produce one or more dissipation voltage pulses having a voltage of opposite sign to the one or more storage pulses, that cause dissipation of charge stored in the dielectric layer. Further disclosed are a memory and a method of electronically storing and reading information, both utilizing the organic-based polarizable gate transistor apparatus.

Switch mode power supply with reduced switching losses

Abstract: The invention relates to a switching transistor presenting reduced switching losses. In the switching transistor, output capacitance is very high when drain/source voltages are low. As the drain/source voltage increases, the capacitance falls to such low values that the energy stored in the transistor becomes very low.

Semiconductor device with CMOS-field-effect transistors having improved drain current characteristics

Abstract: The present invention provides a semiconductor device including n-channel field effect transistors and p-channel field effect transistors all of which have excellent drain current characteristics. In a semiconductor device including an n-channel field effect transistor 10 and a p-channel field effect transistor 30 , a stress control film 19 covering a gate electrode 15 of the n-channel field effect transistor 10 undergoes film stress mainly composed of tensile stress. A stress control film 39 covering a gate electrode 15 of the p-channel field effect transistor 30 undergoes film stress mainly caused by compression stress compared to the film 19 of the n-channel field effect transistor 10 . Accordingly, drain current is expected to be improved in both the n-channel field effect transistor and the p-channel field effect transistor. Consequently, the characteristics can be generally improved.

Driving circuit of current driven element, driving method and image display device

Abstract: PROBLEM TO BE SOLVED: To reduce the adverse effect caused by a parasitic capacitor connected to a signal line of a driving circuit which drives current driven elements such as organic EL (light emitting) being assembled into an active matrix type image display device or the like and to drive the elements with an appropriate current even though a signal current is minute. SOLUTION: An auxiliary transistor 12 having an n times current driving capability of a driving transistor 7 is connected to the transistor 7 in parallel. In a portion (an acceleration interval) of a selection interval, a drain current is made to flow in the transistor 12 also and a signal current itself, which flows in a signal line 3, is made to (n+1) times. COPYRIGHT: (C)2003,JPO

Circuits and methods for a static random access memory using vertical transistors

Abstract: A memory cell. The memory cell has a flip-flop that includes a cross-coupled pair of inverters. The inverters each include a pair of complementary, vertical transistors. A gate contact interconnects the gates of the inverters and acts as the input of the inverter. A shunt interconnects a first source/drain region of the complementary transistors and acts as the output of the inverter. A first vertical, access transistor is also included. The first vertical, access transistor has a gate that is coupled to a word line, a first source/drain region that is coupled to the output of one of the inverters, and a second source/drain region that is coupled to a first bit line. A second vertical, access transistor is also provided. The second vertical, access transistor has a gate that is coupled to the word line, a first source/drain region that is coupled to the output of the other inverter, and a second source/drain region that is coupled to a second bit line.

Charge-pumping circuits for a low-supply voltage

Abstract: The present invention relates to a charge-pumping circuit for low-supply voltage. A small charge-pumping circuit was added at the gates of the original Dickson charge-pumping circuit's each stage for bias voltage and the first transistor group was added between well and gate. The second transistor group was added between the gate and drain of original transistor. Thus, the charge-pumping circuit for low-supply voltage can supply a higher positive or negative voltage.

Symmetrical non-volatile memory array architecture without neighbor effect

Abstract: A method is provided for reading a first non-volatile memory transistor in an array of non-volatile memory transistors, wherein the first non-volatile memory transistor has a drain coupled to a source of a neighbor non-volatile memory transistor. The method includes the steps of (1) applying a read voltage to the gates of the first and neighbor non-volatile memory transistors, (2) applying a source voltage (Vs) to a source of the first non-volatile memory transistor, (3) applying a drain voltage (Vd) to the drain of the first non-volatile memory transistor and the source of the neighbor non-volatile memory transistor, and (4) applying a forcing voltage (Vf) to a drain of the neighbor non-volatile memory transistor. In a particular embodiment, the drain voltage Vd is equal to the forcing voltage Vf. Another embodiment includes the step of applying a second forcing voltage (Vfs) to the source of another neighbor non-volatile memory transistor.

Output buffer with compensated slew rate and delay control

Abstract: A circuit includes a drive transistor coupled between an output and a first potential, a constant current circuit coupled between the gate of the drive transistor and a second potential, and a compensation circuit coupled between the gate of the drive transistor and the first potential. The constant current circuit draws a current from the gate of the drive transistor to the second potential that is substantially independent of process and temperature variations, and therefore turns on the drive transistor at a constant rate, regardless of process and temperature variations. The compensation circuit draws a small current from the gate of the drive transistor to the first potential that is dependent upon process and temperature variations of the drive transistor, and therefore reduces the discharge rate of the gate of the drive transistor according to process and temperature variations of the drive transistor.

Multipeak negative-differential-resistance device by combining single-electron and metal–oxide–semiconductor transistors

Abstract: A multipeak negative-differential-resistance device is proposed. The device comprises a single-electron transistor (SET) and a metal–oxide–semiconductor field-effect transistor (MOSFET), and can, in principle, generate an infinite number of current peaks. Operation of the proposed device is verified at 27 K with a SET fabricated by the pattern-dependent oxidation process and a MOSFET on the same silicon-on-insulator wafer. Six current peaks and a peak-to-valley current ratio of 2.1 are obtained, and multiple-valued memory operation is successfully demonstrated.

Level shifter for use in active matrix display apparatus

Abstract: Between a positive power supply 18 and a negative power supply 19 , a p-channel transistor 11 and an n-channel transistor 14 are connected in series while a p-channel transistor 12 and an n-channel transistor 15 are also connected in series. An inverted input signal *Sig 1 is input to the respective gates of the transistors 11 and 14 , while an input signal Sigl is input to the respective gates of the transistors 12 and 15 . As a result, of a pair of the transistors connected in series, namely either the transistors 11 and 14 or the transistors 12 and 15 , when one transistor turns ON, the other transistor turns OFF. Thus, generation of through currents is prevented.

Power on reset circuit

Abstract: In a power on reset (POR) circuit, when power is turned on, an output signal of an inverter attains an H level and an N channel MOS transistor is rendered conductive. The potential of an input node of the inverter becomes a potential of a power supply voltage divided by a conductive resistance value R1 of a P channel MOS transistor and a conductive resistance value R2 of an N channel MOS transistor. Assuming that the threshold voltage of the inverter is 0.8 V and R1:R2=2:3, then the power supply voltage Vres at the time when signal POR# inverts its level becomes 1.33 V. Thus, this POR circuit can reliably be utilized even in a product designed to operate with 1.5 V incorporating a MOS transistor having a threshold voltage of 0.8 V.

CMOS active pixel sensor using native transistors

Abstract: An active pixel sensor including low threshold voltage transistors advantageously provides an increased output swing over an active pixel sensor of the prior art. The low threshold voltage transistor can be achieved using either a native transistor or a depletion mode transistor. In a process in which a threshold adjustment implant step is separately masked, the active pixel sensor of the present invention can be manufactured with no additional masking requirements. In one embodiment, a low threshold voltage (VTN) allows a transistor acting as a reset switch to operate in the linear region, and allowing the reset switch transistor to share a common supply voltage source with a readout amplifier transistor.

Low power low noise amplifier

Abstract: A low power low noise amplifier achieves a high power gain without increasing power consumption by sharing the bias current. The amplifier is composed of a cascade structure which consists of a parallel connected common source transistor and common gate transistor connected to a common source transistor, an inverter type structure connected to the common source transistor, and structure improving the third-order intermodulation component using the parallel connected common source transistor and common gate transistor.