Showing papers on "Static induction transistor published in 2004"

Organic light emitting device pixel circuit and driving method therefor

Abstract: A pixel circuit in an organic light emitting device capable of realizing high gradation representation by self-compensating a threshold voltage, and a method for driving the same. The pixel circuit includes an electroluminescent element for emitting light in response to an applied driving current. A first transistor delivers a data signal voltage in response to a current scan line signal. A second transistor generates a driving current to drive the electroluminescent element in response to the data signal voltage. A third transistor connects the second transistor in the form of a diode in response to a current scan signal to self-compensate the threshold voltage of the second transistor. A capacitor stores the data signal voltage delivered to the second transistor. A fourth transistor delivers a power supply voltage to the second transistor in response to a current light-emitting signal. A fifth transistor provides the driving current, provided from the second transistor, for the electroluminescent element in response to the current light-emitting signal.

Pixel driver circuit

Abstract: A pixel circuit for use in a display comprising a plurality of pixels is provided. The load-balanced current mirror pixel circuit can compensate for device degradation and/or mismatch, and changing environmental factors like temperature and mechanical strain. The pixel circuit comprises a pixel drive circuit comprising, switching circuitry, a current mirror having a reference transistor and a drive transistor, the reference transistor and the drive transistor each having a first and second node and a gate, the gate of the reference transistor being connected to the gate of the drive transistor; and a capacitor connected between the gate of the reference transistor and a ground potential, and a load connected between the current mirror and a ground potential, the load having a first load element and a second load element, the first load element being connected to the first node of the reference transistor and the second load element being connected to the first node of the drive transistor.

Element substrate and light-emitting device

Abstract: A light emitting device and an element substrate which are capable of suppressing variations in the luminance intensity of a light emitting element among pixels due to characteristic variations of a driving transistor without suppressing off-current of a switching transistor low and increasing storage capacity of a capacitor. According to the invention, a depletion mode transistor is used as a driving transistor. The gate of the driving transistor is fixed in its potential or connected to the source or drain thereof to operate in a saturation region with a constant current flow. A current controlling transistor which operates in a linear region is connected in series to the driving transistor, and a video signal for transmitting a light emission or non-emission of a pixel is inputted to the gate of the current controlling transistor through a switching transistor.

Vertical gain cell

Abstract: A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a source region, and a second vertical MOS transistor merged with the sense transistor. Addressing the second vertical MOS transistor provides a means for changing a potential of the floating body of the sense transistor. The vertical gain cell can be used in a memory array with a read data/bit line and a read data word line coupled to the sense transistor, and with a write data/bit line and a write data word line coupled to the second transistor of the vertical gain cell.

Static Induction Devices with Planar Type Buried Gate

Abstract: Based on the surface-gate and buried-gate structures, a buried-gate structure called the planar type buried-gate (PTBG) structure for static induction devices (SIDs) is proposed. An approach to realize a buried-gate type static induction transistor by conventional planar process technology is presented. Using this structure, it is successfully avoided the second epitaxy with a high degree of difficulty and the complicated mesa process in conventional buried gate. The experimental results demonstrate that this structure is desirable for application in power SIDs. Its advantages are high breakdown voltage and blocking gain.

High voltage ESD protection circuit with low voltage transistors

Abstract: An ESD protection circuit includes a stacked NMOS transistor pair coupled between a pad and a negative voltage supply, with a first transistor's drain connected to the pad and a second transistor's source connected to the negative power supply. A first voltage divider provides reduced voltage from a high voltage positive power supply to a gate of the first transistor, a first diode string coupled between the gates of the first and second transistors, a second diode string with its anode coupled to the pad, an inverter with a source of its PMOS transistor coupled to a cathode of the second diode string and with its NMOS transistor coupled to the negative power supply, an output node of the inverter coupled to a gate of the second transistor, and a RC circuit coupled to an input node of the inverter, for dissipation of ESD current.

Display device of active matrix drive type

Abstract: The invention provides a display device of the active matrix drive type wherein each of pixels 51 comprises an organic EL display element 50 , a drive transistor TR 2 for energizing or deenergizing the EL display element 50 , a write transistor TR 1 to be brought into conduction when impressed with scanning voltage, a capacitance element C 1 to be impressed with data voltage by the conduction of the write transistor TR 1 , and a pulse-width modulation control circuit 90 for on/off-controlling the drive transistor TR 2 by pulse-width-modulating the output voltage of the capacitance element C 1 with ramp voltage. The modulation control circuit 90 comprises an on-control transistor TR 3 and an off-control transistor TR 4.

Method of fabricating a double gate field effect transistor device, and such a double gate field effect transistor device

Abstract: The present invention discloses a method of forming a double gate field effect transistor device, and such a device formed with the method. One starts with a semiconductor-on-insulator substrate, and forms a first gate, source, drain and extensions, and prepares the second gate. Then the substrate is bonded to a second carrier, exposing a second side of the semiconductor layer. Next, an annealing step is performed as a diffusionless annealing, which has the advantage that the semiconductor layer not only has a substantially even thickness, but also has a substantially flat surface. This ensures the best possible annealing action of said annealing step. Very sharp abruptness of the extensions is achieved, with very high activation of the dopants.

Method to improve SRAM performance and stability

Abstract: A technique is disclosed for increasing the width of a transistor ( 300 ) while the transistor itself may be scaled down. The transistor width ( 382 ) is increased by forming recesses ( 352 ) within shallow trench isolation (STI) regions ( 328 ) adjacent to the transistor ( 300 ). The recesses ( 352 ) provide an area that wraps around the transistor and thereby increases the width ( 382 ) of the transistor ( 300 ). This wraparound area provides additional space for dopant atom deposition, which facilitates a reduction in random dopant fluctuation (RDF). In this manner, transistors formed in accordance with one or more aspects of the present invention, may yield improved performance when incorporated into SRAM since the probability that such transistors will be more closely matched is increased.

Design and Demonstration of High Breakdown Voltage GaN High Electron Mobility Transistor (HEMT) Using Field Plate Structure for Power Electronics Applications

Abstract: AlGaN/GaN power high electron mobility transistors (HEMTs) with a breakdown voltage of 600 V are fabricated and demonstrated as switching power devices for motor drive and power supply applications. A high breakdown voltage was realized in the fabricated power-HEMT by the field plate technique and an ultra low on-state resistance of 3.3 mΩcm2, which is 20 times lower than the silicon limit, due to the high critical field of the GaN material and the high mobility in a two-dimensional electron gas channel. A device with the double-field plate structure was also designed using two-dimensional device simulation to increase the breakdown voltage without any increase of the GaN layer thickness.

Radiation image pickup device

Abstract: In a radiation image pickup device including: sensor element for converting radiation into an electrical signal; and a thin film transistor connected to the sensor element, an electrode of the sensor element connected to the thin film transistor is disposed above the thin film transistor, and that the thin film transistor has a top gate type structure in which a semiconductor layer, a gate insulating layer, and a gate electrode layer are laminated in this order on a substrate, so that a channel portion of the thin film transistor is protected by a gate electrode, thereby providing Stable TFT characteristics without undesirable turning ON any of the TFT elements due to the back gate effect by the fluctuation in electric potentials corresponding to outputs from the sensor electrodes, and thereby greatly improving image quality.

High density semiconductor memory cell and memory array using a single transistor and having variable gate oxide breakdown

Abstract: A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+ region in the substrate underlying the gate of the transistor. Further, a gate dielectric of the transistor has a higher breakdown voltage near the source connected to the row wordline than its drain.

Single transistor vertical memory gain cell

Abstract: A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region therebetween. A gate opposes the floating body region and is separated therefrom by a gate oxide on a first side of the vertical transistor. A floating body back gate opposes the floating body region on a second side of the vertical transistor and is separated therefrom by a dielectric to form a body capacitor.

Cascode circuit and integrated circuit having it

Abstract: A cascode circuit includes a first field effect transistor which has a source terminal grounded, a second field effect transistor which has a source terminal connected to a drain terminal of the first field effect transistor, and a first capacitor connected between the source terminal of the first field effect transistor and a gate terminal of the second field effect transistor. The first field effect transistor and the second field effect transistor are cascode-connected successively. A capacitance value of the first capacitor is 0.01 to 10 times that between the gate and source terminals of the second field effect transistor.

Pixel circuit, active matrix system, and display device

Abstract: PROBLEM TO BE SOLVED: To reduce the number of constituting elements in a pixel circuit added with a compensation function with respect to fluctuations in the characteristics of electro-optical elements and fluctuations in the threshold voltages of transistors. SOLUTION: The pixel circuit 101 comprises five n channel thin-film transistors, each composed of the electro-optical element 117, one holding capacitor C 111, a sampling transistor 115, a drive transistor 111, a switching transistor 112, a first detection transistor 114, and a second detection transistor 113. The sampling transistor 115 samples the input signal from a signal line and holds the signal in the holding capacitor C 111. The drive transistor 111 drives the electro-optical element 117 with a current, according to the held signal potential. The first and second detection transistors 114 and 113 detect the threshold voltage of the transistor 111 and hold the detected potential in the holding capacitor C 111, in order to cancel the influence thereof, in advance. COPYRIGHT: (C)2006,JPO&NCIPI

Low capacitance ESD protection device, and integrated circuit including the same

Abstract: A low capacitance ESD protection device. The device comprises a substrate, a well of a first conductivity type in the substrate, a first and second transistor of the first conductivity type respectively on two sides of the well, a guard ring of a second conductivity type in the substrate, surrounding the well, and the first and second transistor, and a doped region of the second conductivity type in the well, wherein profiles of a drain and source region of each of the first and second transistor are un-symmetrical, and an area of the drain region is smaller than that of the source region in each of the first and second transistor.

Apparatus and manufacturing process of carbon nanotube gate field effect transistor

Abstract: The present invention generally relates to an apparatus and method of carbon nanotube (CNT) gate field effect transistor (FET), which is used to replace the current metal gate of transistor for decreasing the gate width greatly. The carbon nanotube has its own intrinsic characters of metal and semiconductor, so it can be the channel, connector or next-level gate of transistor. Furthermore, the transistor has the structure of exchangeable source and drain, and can be defined the specificity by outside wiring.

Current modulation of a hygroscopic insulator organic field-effect transistor

Abstract: We have fabricated solution processable polymer transistors with high conductivity, requiring only a few volts for obtaining good current modulation. The devices can be fabricated and operated in air and the operation is greatly enhanced in humid atmosphere. Devices reach an On∕Off ratio of about 600 and a subthreshold swing of 500mV per decade operating on voltages less than 2V. In this letter the mechanism behind the current modulation is investigated, and we show that the current is modulated through ion-assisted oxidation and reduction of the semiconductor by ions moving vertically in the insulator material to the transistor channel.

Doubly asymmetric double gate transistor structure

Abstract: The present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping one of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. Additionally, the preferred transistor design uses an asymmetric structure that results in reduced gate-to-drain and gate-to-source capacitance. In particular, dimensions of the weak gate, the gate that has a workfunction less attractive to the channel carriers, are reduced such that the weak gate does not overlap the source/drain regions of the transistor. In contrast the strong gate, the gate having a workfunction that causes the inversion layer to form adjacent to it, is formed to slightly overlap the source/drain regions. This asymmetric structure allows for the performance benefits of a double gate design without the increased capacitance that would normally result.

Heterostructure bipolar transistor power amplifier module with dynamic voltage supply for improved efficiency

Abstract: A power amplifier comprises first and second power transistor stages that receive first and second supply voltages, respectively. First and second bias circuits provide the biasing for the first and second power transistor stages, respectively, in response to a reference voltage and a bias voltage.

High voltage double diffused drain MOS transistor with medium operation voltage

Abstract: A method of fabricating a high voltage MOS transistor with a medium operation voltage on a semiconductor wafer. The transistor has a double diffused drain (DDD) and a medium operation voltage such as 6 to 10 volts, which is advantageous for applications having both low and higher operation transistor devices. The second diffusion region of the DDD is self-aligned to the spacer on the sidewalls of the gate and gate dielectric, so that the transistor size may be decreased.

P-channel power MIS field effect transistor and switching circuit

Abstract: In a P-channel power MIS field effect transistor formed on a silicon surface having substantially a (110) plane, a gate insulation film is used which provides a gate-to-source breakdown voltage of 10 V or more, and planarizes the silicon surface, or contains Kr, Ar, or Xe.

Light emissive active matrix display devices with optical feedback effective on the timing, to counteract ageing

Abstract: In an active matrix display, each pixel has a storage capacitor for storing a voltage to be used for addressing a drive transistor. A discharge transistor is provided for discharging the storage capacitor thereby to switch off the drive transistor. The timing of this is controlled by a light-dependent device which is illuminated by the display element. The drive transistor is controlled to provide a constant light output from the display element, and the duration is controlled in dependence on the data voltage. Optical feedback is used to alter further the timing of operation of the discharge transistor to provide ageing compensation of the display element and compensation for changes in the drive transistor.

Transistor structure with a curved channel, memory cell and memory cell array for DRAMs, and methods for fabricating a DRAM

Abstract: A transistor structure having source/drain regions arranged in a horizontal plane along an x axis has a recess structure, which separates the two source/drain regions from one another and increases the effective channel length L eff of the transistor structure. A vertical gate electrode with respect to the horizontal plane extends along the x axis and in this case encloses an active zone of the transistor structure from two sides or completely. The effective channel width W eff is dependent on the depth to which the gate electrode is formed. A memory cell having a selection transistor in accordance with the transistor structure has both a low leakage current and a good switching behavior. By a suitable integration concept, the transistor structure is integrated into a memory cell array of a DRAM having hole trench capacitors or stacked capacitors.

Cascode amplifier structures including wide bandgap field effect transistor with field plates

Abstract: A multi-stage amplifier circuit arranged to take advantage of the desirable characteristics of non-field-plate and field plate transistors when amplifying a signal. One embodiment of a multi-stage amplifier according to the present invention comprises a non-field-plate transistor and a field-plate transistor. The field-plate transistor has at least one field plate arranged to reduce the electric field strength within the field plate transistor during operation. The non-field plate transistor is connected to the field plate transistor, with the non-field-plate providing current gain and the field plate transistor providing voltage gain. In one embodiment the non-field-plate and field plate transistors are coupled together in a cascode arrangement.

Transistor circuit, pixel circuit, display device, and driving method therefor

Abstract: There is provided a transistor circuit having a function to correct fluctuation of a threshold voltage of a thin film transistor. The transistor circuit includes a plurality of thin film transistors (Tr1 to Tr3) formed on a substrate and a wire connecting a transistor gate, source, or drain in such a manner that a predetermined operation can be obtained. During an operation, a forward bias is applied repetitively or continuously to the wire between the gate and the source of the thin film transistor (Tr2). At a timing not disturbing the operation, backward bias is applied to the wire between the gate and the source of the transistor (Tr2) so as to suppress fluctuation of the threshold voltage. More specifically, an additional transistor (Tr3) connected in parallel to the transistor (Tr2) is driven for compensation so as to create the aforementioned timing not disturbing the operation and apply a backward bias to the transistor (Tr2) at the timing created.

Voltage supply with low power and leakage current

Abstract: In a semiconductor integrated circuit device, a circuit block has a first MOS transistor, and a leakage current control circuit having a second MOS transistor and a current source, a source and drain circuit of the second MOS transistor is formed between the power supply line of the circuit block and a voltage point where operating voltage is supplied. This current source is connected to the power supply line and in a first state, the power supply line is driven to a first voltage by the second MOS transistor. In a second state, the power supply line is controlled at a second voltage by current flow in the current source and, the voltage applied across the source and drain of the first MOS transistor in the second state is smaller than the voltage applied across the source and drain of the first MOS transistor in the first state.

Nanotube transistor device

Abstract: A transistor device comprising source and drain regions (S, D), a nanotube structure (2, 3) providing a path for electrical charge carriers between the source and drain regions, and a gate region (4). The nanotube structure has its conduction band structure locally modified in the gate region, e.g. by doping, for controlling the passage of the charge carriers in the path. The device can be used as a flash memory or as a memory element in a DRAM.

High voltage ldmos transistor having an isolated structure

Abstract: A high voltage LDMOS transistor according to the present invention includes a P-field and divided P-fields in an extended drain region of a N-well. The P-field and divided P-fields form junction-fields in the N-well, in which a drift region is fully depleted before breakdown occurs. Therefore, a higher breakdown voltage is achieved and a higher doping density of the N-well is allowed. Higher doping density can effectively reduce the on-resistance of the LDMOS transistor. Furthermore, the N-well generated beneath a source diffusion region provides a low-impedance path for a source region, which restrict the transistor current flow in between a drain region and a source region.

Series terminated CMOS output driver with impedance calibration

Abstract: A differential line driver includes a plurality of driver cells Control logic outputs positive and negative control signals to the driver cells so as to match a combined output impedance of the driver cells at (Vop, Von) Each driver cell includes an input Vip and an input Vin, an output Vop and an output Von, a first PMOS transistor and a first NMOS transistor having gates driven by the input Vip, and a second PMOS transistor and a second NMOS transistor having gates driven by the input Vin A source of the first PMOS transistor is connected to a source of the second PMOS transistor A source of the first NMOS transistor is connected to a source of the second NMOS transistor First and second resistors are connected in series between the first PMOS transistor and the first NMOS transistor, and connected together at Von Third and fourth resistors are connected in series between the second PMOS transistor and the second NMOS transistor, and connected together at Vop A first output switch is driven by a corresponding positive control signal and connected between a supply voltage and the sources of the first and second PMOS transistors A second output switch driven by a corresponding negative control signal and connected between a ground and the sources of the first and second PMOS transistors