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Showing papers on "Static induction transistor published in 2010"


Patent
15 Apr 2010
TL;DR: In this paper, a light emitting device capable of obtaining a certain luminance without influence by the temperature change, and a driving method thereof, is presented, where a current mirror circuit formed by using a transistor is provided for each pixel, such that the drain currents thereof are maintained at proportional values regardless of the load resistance value.
Abstract: The present invention is to provide a light emitting device capable of obtaining a certain luminance without influence by the temperature change, and a driving method thereof. A current mirror circuit formed by using a transistor is provided for each pixel. The first transistor and the second transistor of the current mirror circuit are connected such that the drain currents thereof are maintained at proportional values regardless of the load resistance value. Thereby, a light emitting device capable of controlling the OLED driving current and the luminance of the OLED by controlling the drain current of the first transistor at a value corresponding to a video signal in a driving circuit, and supplying the drain current of the second transistor to the OLED, is provided.

145 citations


Journal ArticleDOI
TL;DR: An ultrasmall single-electron transistor has been made by scaling the size of a fin field-effect transistor structure down to an ultimate limiting form, resulting in the reliable formation of a sub-5 nm Coulomb island as discussed by the authors.
Abstract: An ultrasmall single-electron transistor has been made by scaling the size of a fin field-effect transistor structure down to an ultimate limiting form, resulting in the reliable formation of a sub-5 nm Coulomb island. The charge stability data feature the first exhibition of three and a half clear Coulomb diamonds at 300 K, each showing a high peak-to-valley current ratio. Its charging energy is estimated to be more than one order magnitude larger than the thermal energy at room-temperature. The hybrid literal gate integrated by this single-electron transistor combined with a field-effect transistor displays >5 bit multiswitching behavior at 300 K with a large voltage swing of ∼1 V.

116 citations


Journal ArticleDOI
TL;DR: In this paper, a dual-gate AlGaN/GaN enhancement-mode (E-mode) transistor based on a dualgate structure is presented, which allows the transistor to combine an E-mode behavior with low on-resistance and very high breakdown voltage.
Abstract: In this letter, we present a new AlGaN/GaN enhancement-mode (E-mode) transistor based on a dual-gate structure. The dual gate allows the transistor to combine an E-mode behavior with low on-resistance and very high breakdown voltage. The device utilizes an integrated gate structure with a short gate controlling the threshold voltage and a long gate supporting the high-voltage drop from the drain. Using this new dual-gate technology, AlGaN/GaN E-mode transistors grown on a Si substrate have demonstrated a high threshold voltage of 2.9 V with a maximum drain current of 434 mA/mm and a specific on-resistance of 4.3 m Ω·cm2 at a breakdown voltage of 643 V.

95 citations


Patent
Takashi Miyazawa1
01 Oct 2010
TL;DR: In this paper, a gate of a driving transistor is set to a offset level corresponding to the threshold of the driving transistor by an initializing current flowing between a source and a drain of the driver.
Abstract: A gate of a driving transistor is set to a offset level corresponding to the threshold of the driving transistor by an initializing current flowing between a source and a drain of the driving transistor or a compensating transistor for the driving transistor. A conduction state of the driving transistor is set according to a gate voltage of the gate of the driving transistor that corresponds to a data signal and the threshold of the driving transistor. A current of which a level corresponds to the conduction state and of which the direction is opposite to the direction of the initializing current flows through driving transistor.

92 citations


Patent
27 Dec 2010
TL;DR: In this article, a semiconductor device which can prevent a current from flowing into a display element at a signal writing operation, without increasing power consumption and without changing a potential of a power supply for supplying a current to a load in each row.
Abstract: The present invention provides a semiconductor device which can prevent a current from flowing into a display element at a signal writing operation, without increasing power consumption and without changing a potential of a power supply for supplying a current to a load in each row. When a predetermined current is supplied to a transistor to set a gate-source voltage of the transistor, a potential of a gate terminal of the transistor is adjusted so as to prevent a current from flowing into a load which is connected to a source terminal of the transistor. Thus, a potential of a wire connected to the gate terminal of the transistor is made different from that of a wire connected to a drain terminal of the transistor. At that time, an operation of a transistor is shifted so as to allow a large amount of current to flow, and influences by intersection capacitance parasitic to a wire or the like or wire resistance are hardly caused, and a set operation is conducted quickly.

79 citations


Patent
Nobuaki Tsuji1
20 Dec 2010
TL;DR: In this article, a power amplifying circuit includes a first field effect transistor and a second FET that are connected in series, and are interposed between a high potential power line and a low-potential power line.
Abstract: A power amplifying circuit includes a first field effect transistor and a second field effect transistor that are connected in series, are interposed between a high potential power line and a low potential power line, and drive a load; a predriver that generates, in response to an input signal, gate voltages applied to the first field effect transistor and the second field effect transistor respectively; and a variable power source that supplies source voltages to the high potential power line and the low potential power line respectively, and is configured to control the source voltages.

78 citations


Patent
18 Feb 2010
TL;DR: In this paper, the authors proposed a method for driving a semiconductor device by which influence of variation in threshold voltage and mobility of transistors can be reduced by using an n-channel transistor, a switch for controlling electrical connection between a gate and a first terminal of the transistor, and a display element.
Abstract: To provide a method for driving a semiconductor device, by which influence of variation in threshold voltage and mobility of transistors can be reduced. The semiconductor device includes an n-channel transistor, a switch for controlling electrical connection between a gate and a first terminal of the transistor, a capacitor electrically connected between the gate and a second terminal of the transistor, and a display element. The method has a first period for holding the sum of a voltage corresponding to the threshold voltage of the transistor and an image signal voltage in the capacitor; a second period for turning on the switch so that electric charge held in the capacitor in accordance with the sum of the image signal voltage and the threshold voltage is discharged through the transistor; and a third period for supplying a current to the display element through the transistor after the second period.

77 citations


Patent
22 Jan 2010
TL;DR: In this paper, a gate-connected grounded field plate device was used to minimize the Miller capacitance effect in a high voltage depletion mode tiansistor and a low voltage enhancement mode transistor.
Abstract: A Ill-nitride based high electron mobility transistor is described that has a gate-connected grounded field plate The gate-connected grounded field plate device can minimize the Miller capacitance effect The transistor can be formed as a high voltage depletion mode tiansistor and can be used in combination with a low voltage enhancement-mode transistor to form an assembly that operates as a single high voltage enhancement mode transistor.

74 citations


Patent
Kyung-hoon Chung1
08 Jul 2010
TL;DR: In this paper, an improved pixel circuit including N-type transistors is provided, which includes a light emitting device driven by a driving current according to a gate voltage of a driving transistor.
Abstract: An improved pixel circuit including N-type transistors is provided. The pixel circuit includes a light emitting device driven by a driving current according to a gate voltage of a driving transistor. The pixel circuit also includes a first capacitor, a second transistor for transferring a data signal to a first terminal of the first capacitor in response to a scan control signal, a third transistor for diode-connecting the driving transistor in response to the scan control signal, a fourth transistor for applying a first power voltage to a first electrode of the driving transistor in response to an emission control signal, a fifth transistor for applying a sustain voltage to the first terminal of the first capacitor in response to the emission control signal, and a sixth transistor for applying the first power voltage to a second terminal of the first capacitor in response to an initialization control signal.

65 citations


Patent
28 Jun 2010
TL;DR: In this paper, an embodiment method for power switch temperature control comprises monitoring a power transistor for a delta-temperature fault, and monitoring the power transistor to turn off for an over-time fault.
Abstract: An embodiment method for power switch temperature control comprises monitoring a power transistor for a delta-temperature fault, and monitoring the power transistor for an over-temperature fault. If a delta-temperature fault is detected, then the power transistor is commanded to turn off. If an over-temperature fault is detected, then the power transistor is commanded to turn off, and delta-temperature hysteresis cycling is disabled.

63 citations


Patent
10 Mar 2010
TL;DR: In this article, a suite of innovations are described which may be used in various combinations to minimize dopant diffusion during fabrication of a PMOS or NMOS polycrystalline thin film transistor.
Abstract: Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate length, source and drain dopants will diffuse into the channel, potentially shorting it and ruining the device. A suite of innovations is described which may be used in various combinations to minimize dopant diffusion during fabrication of a PMOS or NMOS polycrystalline thin film transistor, resulting in a highly scalable thin film transistor. This transistor is particularly suitable for use in a monolithic three dimensional array of stacked device levels.

Patent
23 Sep 2010
TL;DR: In this article, the authors proposed a controller that adaptively turns off the low side power transistor when the high and low side transistors are off and an inductor current is non-positive.
Abstract: Systems and methods are disclosed to detect current for an output load with an inductor. The system includes a high side power transistor a low side power transistor coupled to the high side power transistor; and a controller coupled to the high and low side power transistors to provide cycle by cycle conduction of the low side power transistor, said controller adaptively turning off the low side power transistor when the high and low side power transistors are off and an inductor current is non-positive. Adaptation of the turn off of the low side transistor is based on the time position of the detection of the non-positive inductor current and serves to improve the power efficiency of the system.

Patent
04 Aug 2010
TL;DR: In this paper, a semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed.
Abstract: A semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed. By turning OFF a diode-connected transistor 101, the gate terminal of a first transistor 102 is brought into a floating state. At this time, the first transistor 102 is ON and its gate-source voltage is stored in a capacitor. Then, when a potential at the source terminal of the first transistor 102 is increased, a potential at the gate terminal of the first transistor 102 is increased as well by bootstrap effect. As a result, the amplitude of an output signal is prevented from being decreased.

Patent
29 Nov 2010
TL;DR: In this paper, the brightness of the light emitting device is controlled by a programming voltage applied to the gate of the drive transistor, which is adjusted to different levels based on the required brightness of a pixel.
Abstract: A circuit and method to improve energy conservation of an AMOLED display. The display includes a matrix of pixels each having an organic light emitting device coupled to a drive transistor. The brightness of the light emitting device is controlled by a programming voltage applied to the gate of the drive transistor. The supply voltage to the drive transistor is adjusted to different levels based on the required brightness of the pixel. Since the drive transistor operates in saturation mode, especially when maximum brightness is desired, the supply voltage may be reduced while maintaining the same brightness level.

Patent
30 Sep 2010
TL;DR: In this article, the authors provide a semiconductor device and a driving method for enlarging a signal amplitude value as well as increasing a range in which a linear input/output relationship operates while preventing a signal writing-in time from becoming long.
Abstract: To provide a semiconductor device and a driving method of the same that is capable of enlarging a signal amplitude value as well as increasing a range in which a linear input/output relationship operates while preventing a signal writing-in time from becoming long. The semiconductor device having an amplifying transistor and a biasing transistor and the driving method thereof, wherein an electric discharging transistor is provided and pre-discharge is performed.

Patent
Deok-Young Choi1, Yong-Sung Park1, Do-youb Kim1, Soon-Sung Ahn1, In-Ho Choi1 
09 Mar 2010
TL;DR: In this article, a light sensing circuit includes a photodiode including a cathode electrode and an anode electrode, a driving transistor for amplifying the current generated in the photodiodes, a capacitor for storing a first initiation voltage transmitted to the driving transistor, a first switching transistor for compensating for a threshold voltage of the driving transistors corresponding to a current scan signal, and a second switching transistors for transmitting the first initiator voltage corresponding to the current scan signals.
Abstract: A light sensing circuit includes a photodiode including a cathode electrode and an anode electrode and for receiving light from the outside and generating a current corresponding to the received light, a driving transistor for amplifying the current generated in the photodiode, a capacitor for storing a first initiation voltage transmitted to the driving transistor, a first switching transistor for compensating for a threshold voltage of the driving transistor corresponding to a current scan signal, and a second switching transistor for transmitting the first initiation voltage corresponding to the current scan signal.

Patent
26 Oct 2010
TL;DR: In this paper, a thin film transistor whose channel is formed using an amorphous semiconductor is used for a driver circuit formed using only n-channel transistors or p-channel Transistors.
Abstract: One object is, when a thin film transistor whose channel is formed using an amorphous semiconductor is used for a driver circuit formed using only n-channel transistors or p-channel transistors, to provide a driver circuit in which the threshold voltage is compensated in accordance with the degree of change in the threshold voltage. In the driver circuit which includes a unipolar transistor including a first gate and a second gate which are disposed above and below a semiconductor layer with insulating layers provided therebetween, a first signal for controlling switching of the transistor is inputted to the first gate, a second signal for controlling a threshold voltage of the transistor is inputted to the second gate, and the second signal is controlled in accordance with a value of current consumption including a current which flows between a source and a drain of the transistor.

Patent
21 Oct 2010
TL;DR: In this article, a voltage regulator circuit includes a transistor and a capacitor, and an oxide semiconductor layer is used for a channel formation layer, an off-state current is less than or equal to 10 aA/μm.
Abstract: A voltage regulator circuit includes a transistor and a capacitor. The transistor includes a gate, a source, and a drain, a first signal is inputted to one of the source and the drain, a second signal which is a clock signal is inputted to the gate, an oxide semiconductor layer is used for a channel formation layer, and an off-state current is less than or equal to 10 aA/μm. The capacitor includes a first electrode and a second electrode, the first electrode is electrically connected to the other of the source and the drain of the transistor, and a high power source voltage and a low power source voltage are alternately applied to the second electrode.

Patent
William Robert Reohr1, John E. Barth1, Toshiaki Kirihata1, Derek H. Leu1, Donald W. Plass1 
12 Feb 2010
TL;DR: In this paper, the pull-up and pull-down transistors are coupled to a DRAM cell, and the source is coupled to the drain of the pulldown transistor, the drain to the word line and the gate to a pulldown clamp gate signal.
Abstract: A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.

Patent
10 Jun 2010
TL;DR: In this article, a high-voltage semiconductor device and a high voltage integrated circuit device are presented, which achieves low voltage driving and quick response by way of stable high voltage wiring and a low ON voltage.
Abstract: Aspects of the present invention provide a high-voltage semiconductor device and a high voltage integrated circuit device while minimizing or eliminating the need for the addition of back surface steps. Aspects of the invention provide a high-voltage semiconductor device that achieves, low voltage driving and quick response by way of stable high voltage wiring and a low ON voltage. In some aspects of the invention, a high-voltage semiconductor device can include a semiconductor layer is formed on a support substrate interposing an embedded oxide film therebetween. A high potential side second stage transistor and a low potential side first stage transistor surrounding the second stage transistor are formed on the surface region of the semiconductor layer. The source electrode of the second stage transistor is connected to the drain electrode of the first stage transistor. A drain electrode of the second stage transistor is connected to a drain pad.

Patent
27 Aug 2010
TL;DR: In this paper, the driver circuit includes a static shift register including an inverter circuit having a first transistor and a second transistor, and a switch including a third transistor, which are depletion-mode transistors.
Abstract: An object of the present invention is to provide a driver circuit including a normally-on thin film transistor, which driver circuit ensures a small malfunction and highly reliable operation. The driver circuit includes a static shift register including an inverter circuit having a first transistor and a second transistor, and a switch including a third transistor. The first to third transistors each include a semiconductor layer of an oxide semiconductor and are depletion-mode transistors. An amplitude voltage of clock signals for driving the third transistor is higher than a power supply voltage for driving the inverter circuit.

Patent
04 Feb 2010
TL;DR: In this paper, a current generation circuit with a metal oxide semiconductor (MOS) transistor whose gate and drain terminals are connected to each other and which operates in a weak inversion region is presented.
Abstract: PROBLEM TO BE SOLVED: To provide a power supply integrated circuit including an overheat protection circuit with a high detection accuracy. SOLUTION: The overheat protection circuit includes a current generation circuit which is provided with a first metal oxide semiconductor (MOS) transistor whose gate and drain terminals are connected to each other and which operates in a weak inversion region; a second MOS transistor whose gate terminal is connected to that of the first MOS transistor and which has a conductivity type identical to that of the first MOS transistor and operates in a weak inversion region; and a first resistive element connected to the source terminal of the second MOS transistor, and a comparator which compares the reference voltage having positive temperature characteristics with a temperature voltage having negative temperature characteristics, both of which are obtained based on a current generated by the current generation circuit. COPYRIGHT: (C)2011,JPO&INPIT

Patent
02 Jul 2010
TL;DR: A two transistor NOR flash memory cell has symmetrical source and drain structure manufactured by a NAND-based manufacturing process as discussed by the authors, which includes a storage transistor consisting of a double-poly NMOS floating gate transistor and an access transistor made of a single-poly poly 1 or poly 2 NMOS transistor.
Abstract: A two transistor NOR flash memory cell has symmetrical source and drain structure manufactured by a NAND-based manufacturing process. The flash cell comprises a storage transistor made of a double-poly NMOS floating gate transistor and an access transistor made of a double-poly NMOS floating gate transistor, a poly1 NMOS transistor with poly1 and poly2 being shorted or a single-poly poly1 or poly2 NMOS transistor. The flash cell is programmed and erased by using a Fowler-Nordheim channel tunneling scheme. A NAND-based flash memory device includes an array of the flash cells arranged with parallel bit lines and source lines that are perpendicular to word lines. Write-row-decoder and read-row-decoder are designed for the flash memory device to provide appropriate voltages for the flash memory array in pre-program with verify, erase with verify, program and read operations in the unit of page, block, sector or chip.

Patent
22 Dec 2010
TL;DR: A pull-down MOSFET (110) is coupled between a drain and gate of a main switch transistor (102) in a switching type DC-to-DC power converter as mentioned in this paper.
Abstract: A pull-down MOSFET (110) is coupled between a drain and gate of a MOSFET main switch transistor (102) in a switching type DC-to-DC power converter. A gate of the pull-down MOSFET (110) is coupled to the drain of the main switch transistor (102) by a capacitor 118 and is connected to a source of the main switch transistor (102) by a resistor (120). The pull-down MOSFET (110) is operated by capacitive coupling to the voltage drop across the main switch transistor (102) and can be used to hold the gate of the main switch transistor (102) at or near its source potential to avoid or reduce unintentional turn-on of the main switch transistor (102) by the Miller effect.

Patent
Sam-Il Han1
15 Sep 2010
TL;DR: In this article, a pixel, a display device using the same, and a driving method thereof, sufficient time to compensate the threshold voltage of the driving transistor of the pixel may be obtained under high resolution and high frequency driving to realize a displaydevice of high image quality.
Abstract: A pixel, a display device using the same, and a driving method thereof are disclosed. According to exemplary embodiments of the pixel, the display device including the same, and the driving method thereof, sufficient time to compensate the threshold voltage of the driving transistor of the pixel may be obtained under high resolution and high frequency driving to realize a display device of high image quality.

Patent
25 Jun 2010
TL;DR: In this article, an improved voltage reference generator is proposed, which consists of a first transistor having a gate electrode biased to place the first transistor in a weak inversion mode; and a second transistor connected in series with the first one and having a second gate electrode bias to place it in a weaker inversion.
Abstract: An improved voltage reference generator is provided. The voltage reference generator comprises: a first transistor having a gate electrode biased to place the first transistor in a weak inversion mode; and a second transistor connected in series with said first transistor and having a gate electrode biased to place the second transistor in a weak inversion mode, where the threshold voltage of the first transistor is smaller than the threshold voltage of the second transistor and the gate electrode of the second transistor is electrically coupled to a drain electrode of the second transistor and the source electrode of the first transistor to form an output for a reference voltage.

Patent
13 Apr 2010
TL;DR: In this paper, a coupling capacitor has one end connected to a data line and the other end is connected to an organic EL element via a light emission control transistor (LEC).
Abstract: In order to efficiently execute threshold value compensation for a driving transistor, a coupling capacitor (6) has one end connected to a data line (8). Another end of the coupling capacitor (6) is connected to a selection transistor (3) and one end of a reset transistor (4). A control terminal of a driving transistor (2) is connected to the other end of the selection transistor (3), and an organic EL element (1) is connected to this driving transistor via a light emission control transistor (5). A data voltage, corresponding to a gradation signal supplied to the data line (8), is written to a storage capacitor (7) via the coupling capacitor (6), and with the selection transistor (3) and the light emission control transistor (5) in an off state and the reset transistor (4) turned on, a compensation voltage corresponding to a degree of mobility of the driving transistor (2) is written to the coupling capacitor (6).

Patent
30 Dec 2010
TL;DR: In this article, a current sensing circuit with a load transistor and a sense transistor coupled to the load transistor is described. But the circuit is not shown to be suitable for the measurement of the load current.
Abstract: A current sensing circuit arrangement is disclosed. The circuit arrangement includes a load transistor for controlling a load current to a load being coupled to a drain electrode of the load transistor. A sense transistor is coupled to the load transistor. The sense transistor has a drain electrode that provides a measurement current representative of the load current. The load transistor and the sense transistor are field effect transistors having a common source electrode. A measurement circuit is configured to receive the measurement current from the sense transistor and to generate an output signal therefrom, the output signal being representative of the load current.

Patent
29 Nov 2010
TL;DR: In this article, the authors present a transistor, a method of manufacturing the transistor and an electronic device including the transistor, provided that the transistor is a source, a drain, and a gate.
Abstract: Provided are a transistor, a method of manufacturing the transistor, and an electronic device including the transistor. The transistor may include a passivation layer on a channel layer, a source, a drain, and a gate, wherein the component of the passivation layer is varied in a height direction. The passivation layer may have a multi-layer structure including a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer sequentially stacked. The channel layer may include an oxide semiconductor.

Patent
Jong-Hyun Choi1, Sung Ho Kim1
13 Jan 2010
TL;DR: In this paper, the shared gate electrode is used as a doping or implantation mask in the formation of the source and drain regions of the poly-silicon transistor, where both transistors share the same gate electrode.
Abstract: A CMOS thin film transistor arrangement including a PMOS poly-silicon thin film transistor having a top gate configuration and a NMOS oxide thin film transistor having an inverted staggered bottom gate configuration where both transistors share the same gate electrode. The shared gate electrode is used as a doping or implantation mask in the formation of the source and drain regions of the poly-silicon transistor.