Showing papers on "Static induction transistor published in 2014"

Semiconductor device and method for driving the same

Abstract: A semiconductor device includes a photodiode, a first transistor, and a second transistor The photodiode has a function of supplying a charge corresponding to incident light to a gate of the first transistor, the first transistor has a function of accumulating the charge supplied to the gate, and the second transistor has a function of retaining the charge accumulated in the gate of the first transistor The second transistor includes an oxide semiconductor

Display apparatus, method of driving a display, and electronic device

Abstract: In a display apparatus including a switching transistor, a correction voltage for eliminating an effect of a variation in a characteristic of a driving transistor is stored in a storage capacitor. The switching transistor is disposed between one current terminal of the driving transistor and a light emitting element. The switching transistor turns off during the non-light emission period thereby to electrically disconnect the light emitting element from the one current terminal of the driving transistor thereby preventing a leakage current from flowing through the light emitting element during the period in which the correction unit operates, and thus preventing the correction voltage from having an error due to the leakage current.

The Super-Lattice Castellated Field Effect Transistor (SLCFET): A novel high performance Transistor topology ideal for RF switching

Abstract: NGES reports the development of a novel transistor structure based on a GaN super-lattice channel with a 3D gate, named the SLCFET (Super-Lattice Castellated Field Effect Transistor). Transistor measurements provided median values of I MAX >2.7 A/mm, V PINCH = −8V, with R ON =0.41 Ω-mm and C OFF =0.19 pF/mm, for an RF switch FOM of F CO =2.1 THz.

A New Slit-Type Vacuum-Channel Transistor

Abstract: A new vacuum-channel transistor with a carbon nanotube cathode and nanometer-scale channel length—called a slit-type vacuum-channel transistor —is proposed and investigated. The suggested device structure features distinguishable cutoff, linear, and saturation regions with a negligible gate leakage current. Its channel length is almost the same as the mean free path of carriers in air, which suggests that the device can operate not only in vacuum but also in air, without any performance degradation. Because of its geometrical characteristics, it is possible for this device to be operated when the anode bias is almost the same as the gate bias with negligible oxide leakage. Therefore, the device can be used as an elemental device component in digital integrated circuits.

RF power transistor circuits

Abstract: A radio frequency (RF) power transistor circuit includes a power transistor and a decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, a first current electrode for providing an RF output signal at an output terminal, and a second current electrode coupled to a voltage reference. The decoupling circuit includes a first inductive element, a first resistor, and a first capacitor coupled together in series between the first current electrode of the power transistor and the voltage reference. The decoupling circuit is for dampening a resonance at a frequency lower than an RF frequency.

Replacement metal gate transistor with controlled threshold voltage

Abstract: A method and structure for a semiconductor device includes a semiconductor substrate and an N-channel transistor and a P-channel transistor provided on the semiconductor substrate. Each of the N-channel transistor and the P-channel transistor has a gate dielectric film on the semiconductor substrate, and a gate electrode is formed on the gate dielectric. The gate electrode comprises a metal conductive layer. The oxygen concentration in the metal conductive layer for the N-channel transistor is different from that for the P-channel transistor.

Pixel compensating circuit and method of organic light emitting display

Abstract: A pixel compensating circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a driving transistor, a first capacitor, and an organic light emitting diode element. The first transistor controls transmission of a data signal to a first electrode plate of the first capacitor. The second transistor controls transmission of a reference voltage signal to the first electrode plate of the first capacitor. The driving transistor determines an amount of a driving current. The third transistor controls connection and disconnection between the gate electrode and a drain electrode of the driving transistor. The fourth transistor transmits the driving current from the driving transistor to the organic light emitting diode element. The fifth transistor controls transmission of a supply voltage to the source electrode of the driving transistor; and the organic light emitting diode element emits light in response to the driving current.

Amplifiers with inductive degeneration and configurable gain and input matching

Abstract: Amplifiers with inductive degeneration and configurable gain and input matching are disclosed. In an exemplary design, an apparatus includes a gain transistor, an inductor, and an input matching circuit for an amplifier. The gain transistor has a variable gain determined based on its bias current. The inductor is coupled between the gain transistor and circuit ground. The input matching circuit is selectively coupled to the gain transistor based on the variable gain of the gain transistor. For example, the input matching circuit may be coupled to the gain transistor in a low-gain mode and decoupled from the gain transistor in the high-gain mode. In an exemplary design, the input matching circuit includes a resistor, a capacitor, and a second transistor coupled in series. The resistor is used for input matching of the amplifier. The second transistor couples or decouples the resistor to or from the gain transistor.

Non-volatile ternary content-addressable memory 4t2r cell with rc-delay search

Abstract: The 4T2R cell comprises a write transistor, a first variable resistive element, a first transistor, a second variable resistive element, a second transistor, and a charge control transistor. The first transistor is electrically coupled to the first variable resistive element in series, and the second transistor is electrically coupled to the second variable resistive element in series, for providing search paths. For operating in a search phase, a pulse voltage is applied across the gate electrode and the source electrode of the first transistor (or across the gate electrode and the source electrode of the second transistor) for determining whether the gate voltage of the charge control transistor changes larger than a match threshold during the period of the pulse. Different RC-delay of the variable resistive elements controlling the voltage change speed of the gate voltage of the charge control transistor determines the matching result.

Organic light emitting display and repairing method of the same

Abstract: A repair path is established between a sub-pixel with a defective drive transistor and another sub-pixel with an operable drive transistor to connect storage capacitors in the two sub-pixels in parallel. Another repair path is established to operate a light emitting device by the operable drive transistor of the second sub-pixel. Terminals of the storage capacitors in the two pixels are connected to a gate of the operable drive transistor. The voltage at the terminals of the storage capacitors are maintained above the threshold voltage of the operable drive transistor is switched on for a longer time due to the combined capacitance of the two storage capacitance. Hence, the sub-pixel with the defective drive transistor and the other sub-pixel of the operable drive transistor remain turned on for a longer time. Hence, despite providing a lower level of current to each of the light emitting devices in the two sub-pixels, the intensity of light produced remains relatively high due to increased turn on time of the operable drive transistor.

System and method for a switch having a normally-on transistor and a normally-off transistor

Abstract: In accordance with an embodiment, a method includes conducting a reverse current through a first switch that includes a normally-on transistor coupled in series with a normally-off transistor between a first switch node and a second switch node. While conducting the reverse current, the first switch is turned-off by turning-off the normally-off transistor via a control node of the normally-off transistor and reducing a drive voltage of the normally-on transistor by decreasing a voltage between the control node of the normally-on transistor and a reference node of the normally-on transistor. After turning-off the first switch, a second switch coupled to the first switch is turned on.

Drive circuit, display device, and drive method

Abstract: A drive circuit for a light emitting element which can correct a threshold voltage of a drive transistor between two reference voltages without a reset power supply. The drive circuit includes a light emitting element, a drive transistor for controlling an amount of current, a first switching element that is arranged between the light emitting element and the drive transistor, a second switching element that is arranged between the drive transistor and the second reference voltage, a third switching element that is arranged between a gate, and one of a source and a drain of the drive transistor, a fourth switching element that is connected to the other of the source and the drain of the drive transistor, and controls input of signal voltage, and a first capacitor connected to the gate of the drive transistor.

Pixel driving circuit of organic light emitting display

Abstract: An OLED pixel driving circuit includes a first transistor controlled by a scan driving signal to control transmission of a data signal and a reference voltage signal to a first electrode plate of a capacitor; a second transistor electrically connected to a second electrode plate of the capacitor to determine magnitude of a driving current, where the driving current is determined by a voltage difference between a gate and a drain of the second transistor; a third transistor electrically connected to the second electrode plate of the capacitor and the second transistor and controlled by a first driving signal to control conduction or cut-off between the gate and the drain of the second transistor; and a fourth transistor electrically connected to the second transistor and the third transistor and controlled by a second driving signal to control transmission of the driving current to an organic light emitting element.

Solid-state imaging device and method of manufacturing the device

Abstract: Each unit pixel includes a photoelectric converter, an n-type impurity region forming an accumulation diode together with the semiconductor region, the accumulation diode accumulating a signal charge generated by the photoelectric converter, an amplifier transistor including a gate electrode electrically connected to the impurity region, and an isolation region formed around the amplifier transistor and implanted with p-type impurities. The amplifier transistor includes an n-type source/drain region formed between the gate electrode and the isolation region, and a channel region formed under the gate electrode. A gap in the isolation region is, in a gate width direction, wider at a portion including the channel region than at a portion including the source/drain region.

Image sensor pixel cell with global shutter having narrow spacing between gates

Abstract: A pixel cell includes a photodiode, a storage transistor, a transfer transistor and an output transistor disposed in a semiconductor substrate. The transfer transistor selectively transfers image charge accumulated in the photodiode from the photodiode to the storage transistor. The output transistor selectively transfers the image charge from the storage transistor to a readout node. A first isolation fence is disposed over the semiconductor substrate separating a transfer gate of the transfer transistor from a storage gate of the storage transistor. A second isolation fence is disposed over the semiconductor substrate separating the storage gate from an output gate of the output transistor. Thicknesses of the first and second isolation fences are substantially equal to spacing distances between the transfer gate and the storage gate, and between the storage gate and the output gate, respectively.

LDMOS FinFET device using a long channel region and method of manufacture

Abstract: A FinFET includes a semiconductor fin supporting a first transistor and a second transistor. A first transistor gate electrode extends over a first channel region of the fin and a second transistor gate electrode extends over a second channel region of the fin. Epitaxial growth material on a top of the fin forms a raised source region on a first side of the first transistor gate electrode, an intermediate region between a second side of the first transistor gate electrode and a first side of the second transistor gate electrode, and a raised drain region on a second side of the second transistor gate electrode. The first and second transistor gate electrodes are short circuit connected to each other, with the first transistor configured to have a first threshold voltage and the second transistor configured to have a second threshold voltage different from the first threshold voltage.

Integration method for fabrication of metal gate based multiple threshold voltage devices and circuits

Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.

New insights about oxide breakdown occurrence at circuit level

Abstract: With device scaling, electric fields across the gate oxide have increased and supply voltages have been reduced not as much as the gate-oxide thickness, intensifying the probability of dielectric breakdown events for transistors. In this context, the more the oxide thickness is reduced, the more the oxide breakdown degradation is progressive. However, the first breakdown event does not always cause a functional failure in digital circuits. As a consequence, relaxation of the predicted lifetime could be accounted at circuit level with respect to the area scaling. First, this paper deals with characterization of soft breakdown events at device level. Post-breakdown degraded parameters and their dispersion are identified and quantified. Then a transistor-level model of breakdown is presented; it handles distributions of Time to Breakdown, breakdown spots localization and parameters degradation (ΔV t , evolution of I d /I s , ΔI g , ΔI dlin ...). This model is implemented in API, it takes into account both BTI and oxide breakdown degradation contributions and is calibrated for a range of breakdown severity used at circuit level. A custom digital circuit has been implemented to measure the impact of multiple oxide breakdowns on static current and oscillation frequency. The theoretical models of multiple oxide breakdown events reproduce properly the experimental behavior. Finally the case of hard breakdown events in a data path is investigated and the impact on percentage errors is discussed.

Programmable current source for a time of flight 3D image sensor

Abstract: A programmable current source for use with a time of flight pixel cell includes a first transistor. A current through the first transistor is responsive to a gate-source voltage of the first transistor. A current control circuit is coupled to the first transistor and coupled to a reference current source to selectively couple a reference current of the reference current source through the first transistor during a sample operation. A sample and hold circuit is coupled to the first transistor to sample a gate-source voltage of the first transistor during the sample operation. The sample and hold circuit is coupled to hold the gate-source voltage during a hold operation after the sample operation substantially equal to the gate-source voltage during the sample operation. A hold current through the first transistor during the hold operation is substantially equal to the reference current.

SUB 3-micron gap microplasma fet with 50 V turn-on voltage

Abstract: This work reports the smallest microplasma field-effect transistor reported till date that operates with a low turn-on voltage of ~50V dc; a more than 3x reduction in the turn-on voltage compared to earlier reported work. Our previous work used plasma from an external source to operate the transistor while in the present work we use rf or dc voltage to directly generate plasma in the transistor channel and use dc gate field effect to control the device conduction. The reduction in turn-on voltage is achieved by a small plasma cavity of 1.5μm gap width.

Static random access memory (SRAM) cells including vertical channel transistors

Abstract: A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor.

Flipped gate voltage reference and method of using

Abstract: A voltage reference includes a flipped gate transistor configured to receive a first current. The voltage reference further includes a first transistor configured to receive a second current, the first transistor having a first leakage current, wherein the first transistor is connected with the flipped gate transistor in a Vgs subtractive arrangement. The voltage reference further includes an output node configured to output a reference voltage, the output node connected to the first transistor. The voltage reference further includes a second transistor connected to the output node, the second transistor having a second leakage current, wherein the first leakage current is substantially equal to the second leakage current.

Scan lines driver and organic light emmiting display device using the same

Abstract: In a scan lines driver that is used for driving scan lines of an organic light emitting diodes (OLED) display, a large voltage drop can develop between the gate or source of one of its transistors and the corresponding drain during a scan signal outputting period. This large voltage drop can excessively stress the one transistor. However, in accordance with the present disclosure, a voltage drop dissipating, second transistor is provided in series with the first transistor for absorbing part of the large voltage drop and thus reducing the stress that is applied to the first transistor.

Push-Pull Microphone Buffer

Abstract: A buffer is coupled to an acoustic motor. The buffer has an input and an output. The input has an input voltage and the output has an output voltage. The buffer is coupled to a load. The buffer includes an input transistor and push-pull transistor circuitry. The input transistor has a gate, a source, and a drain, a gate-to-source capacitance, and an area. The push-pull transistor circuitry is coupled to the input transistor. Under a first set of operating conditions, the gate to source voltage of the input transistor remains constant and the output voltage is a buffered copy of the input voltage. Under a second set of operating conditions, the push-pull transistor circuitry selectively sinks or sources additional current to the load so that linearity of buffer operation is provided. A gate-to-drain capacitance of the input transistor is buffered allowing the area of the input transistor to be increased without reducing the gain of the motor.

Display device, driving method for display device and electronic apparatus

Abstract: A display device includes a pixel array unit formed by disposing pixel circuits having a P-channel type drive transistor that drives a light-emitting unit, a sampling transistor that applies a signal voltage, a light emission control transistor that controls emission/non-emission of the light-emitting unit, a storage capacitor that is connected between a gate electrode and a source electrode of the drive transistor and an auxiliary capacitor that is connected to the source electrode, and a drive unit that, during threshold correction, respectively applies a first voltage and a second voltage to the source electrode of the drive transistor and the gate electrode thereof, the difference between the first voltage and the second voltage being less than a threshold voltage of the drive transistor, and subsequently performs driving that applies a standard voltage used in threshold correction to the gate electrode when the source electrode is in a floating state.

Shift register circuit

Abstract: A shift register circuit including a logic circuit capable of controlling the threshold voltage of a transistor and outputting a signal corresponding to an input signal by changing only the potential of a back gate without changing the potential of a gate is provided. In a shift register circuit including a logic circuit with a first transistor and a second transistor having the same conductivity type, a first gate electrode of the first transistor is connected to a source electrode or a drain electrode of the first transistor, an input signal is supplied to a second gate electrode of the first transistor, a clock signal is supplied to a gate electrode of the second transistor, and the first gate electrode and the gate electrode are formed from the same layer.

Current mirror circuit and charge pump circuit

Abstract: A current mirror circuit includes: a reference current circuit including a reference transistor and a constant current source coupled between a high potential source and a low potential source; a first proportional current circuit, including a first transistor that forms a first current mirror circuit with the reference transistor, to generate a first current having a first ratio to a reference current of the reference current circuit; a second proportional current circuit, including a second transistor that forms a second current mirror circuit with the reference transistor, to generate a second current having a second ratio to the reference current; a comparison circuit to output a difference between a drain voltage of the first transistor and a drain voltage of the second transistor; and a current adjustment transistor coupled to a drain of the second transistor and including a gate to which an output of the comparison circuit is applied.

Method of forming electronic components with increased reliability

Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.

Method and circuitry for controlling a depletion-mode transistor

Abstract: In described examples, a first transistor has: a drain coupled to a source of a depletion-mode transistor; a source coupled to a first voltage node; and a gate coupled to a control node. A second transistor has: a drain coupled to a gate of the depletion-mode transistor; a source coupled to the first voltage node; and a gate coupled through at least one first logic device to an input node. A third transistor has: a drain coupled to the gate of the depletion-mode transistor; a source coupled to a second voltage node; and a gate coupled through at least one second logic device to the input node.

Semiconductor device and driving system

Abstract: An output MOS transistor has a drain connected with a power supply and a source connected with an output terminal. The short-circuit MOS transistor has a source connected with the output terminal. The short-circuit MOS transistor is formed in a semiconductor substrate connected with the power supply. A switching device is formed in a semiconductor region which is formed in the semiconductor substrate, and contains a first diffusion layer connected with the gate of the output MOS transistor and a second diffusion layer formed in the semiconductor region and connected with the drain of the short-circuit MOS transistor.