Showing papers on "Static induction transistor published in 2016"

MoS2 Tribotronic Transistor for Smart Tactile Switch

Abstract: A novel tribotronic transistor has been developed by vertically coupling a single-electrode mode triboelectric nanogenerator and a MoS2 field effect transistor. Once an external material contacts with or separates from the device, negative charges are induced by triboelectrification on the surface of the polymer frictional layer, which act as a “gate” voltage to modulate the carrier transport in the MoS2 channel instead of the conventional applied gate voltage; the drain-source current can be tuned in the range of 1.56–15.74 μA, for nearly ten times. The application of this MoS2 tribotronic transistor for the active smart tactile switch is also demonstrated, in which the on/off ratio can reach as high as ≈16 when a finger touches the device and the increased drain-source current is sufficient to light two light-emitting diodes. This work may provide a technique route to utilize the 2D materials based tribotronic transistors in MEMS, nanorobotics, and human–machine interfacing.

High frequency performance of dual metal gate vertical tunnel field effect transistor based on work function engineering

Abstract: A novel dual metal gate doping-less vertical tunnel field effect transistor (D-VTFET) on silicon body, using work function engineering is proposed. The proposed structure does not required impurity doping for formation of the drain and the source regions. In this concern, source and drain regions are formed by selecting appropriate work-function of metal electrode. The source and drain regions are not formed by conventional ways of ion implantation or diffusion. Hence, proposed structure is immune greatly to the process variation, issues of doping control and random dopant fluctuations which are serious problems in ultrathin silicon devices. For further improvement in ON state current and analogue/RF figures of merit dual work function of single gate material is considered. The electrical characteristics of the proposed device with the D-VTFET are simulated and compared.

Flexible 3D Graphene Transistors with Ionogel Dielectric for Low-Voltage Operation and High Current Carrying Capacity

Abstract: In this paper, an ionogel-gated flexible 3D graphene transistor made from graphene foam, consisting of a network of few layers graphene, is reported. The presented transistor, fabricated on thin, 28 μm parylene, flexible substrate, demonstrates low-voltage operation (≤2.5 V) and exhibits 4.78 times higher current capacity than previously reported liquid-gated 3D graphene transistor fabricated on glass substrate. This is also 26.72 times higher current capacity (93 mA at 2 V applied VD) than the equivalent long channel (≈600 μm) 2D transistor device. The high current capacity and low operating voltage of this transistor are attributed to higher surface area, 3D structure of the transistor, and the high capacitive coupling between the ionogel gate and graphene. The transistor is thoroughly characterized for I–V characteristics and evaluated for circuit functionality. As a representative example, high current capacity was demonstrated by driving an LED where brightness depends on the current level through them which was tuned using the gate bias of the 3D transistor. The proposed transistor may find application in large-area electronics for interactive displays and for large-area sensors in structural health monitoring.

Driving circuit of active-matrix organic light-emitting diode with hybrid transistors

Abstract: A driving circuit includes a current drive unit and a reset compensation and light emitting control circuit. The current drive unit includes a first transistor and a second transistor. The first transistor and the second transistor are connected in series, wherein the first transistor and the second transistor include a silicon semiconductor layer. The reset compensation and light emitting control circuit is coupled to the current drive unit. The reset compensation and light emitting control circuit includes a third transistor connected to a control terminal of the first transistor, wherein the third transistor is an oxide semiconductor transistor.

Trenched vertical power field-effect transistors with improved on-resistance and breakdown voltage

Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

Small signal modelling approach for submillimeter wave III–V HEMTs with analysation and optimization possibilities

Abstract: In this paper we present a new small signal multiport modelling approach for III–V High Electron Mobility Transistors (HEMT) that is capable for internal transistor analysation and optimization as well as scaleable in gate width and finger-number. The new model decomposes the planar transistor structure into single multiport elements that are separately described by electrical equivalent circuits and connected to each other over discrete ports. With this new modelling topology we only need to extract a couple of multiport elements to predict the correct behavior for a high amount of different planar transistor structures. This point gives the circuit designer a wide range of possibilities to analyze and optimize a given transistor structure according to special needs, like low-noise, input-output matching or cryogenic behavior on a computer based level.

Asymmetric split-gate ambipolar transistor and its circuit application to complementary inverter

Abstract: Using a concept of asymmetric side gate and main gate, it is shown that it is possible to realize unipolar transport (both p-type and n-type) in a thin-film transistor with a high-performance ambipolar polymer semiconductor. In a complementary inverter, this results in higher noise margin and DC gain.

Self-Destructible Fin Flip-Flop Actuated Channel Transistor

Abstract: A self-destructible fin flip-flop actuated channel transistor is presented as a candidate for transient electronics. The device uses a movable fin anchored on the source and drain pads with two independent gates on each side of the fin. The fin is in contact with a primary gate during normal operation providing the performance of a single-gate thin-body transistor. When death of the device is desired, a trigger voltage applied to a trigger gate mechanically shatters the source/drain extension region of the fin due to electrostatic bending stress. The self-destruction operation results in the formation of an open circuit at the individual transistor level, terminating the designed function of the chip. The present device can be used in security, military, and consumer applications to protect from malicious attempts to operate the system or gain access to sensitive information.

3d transistor having a gate stack including a ferroelectric film

Abstract: A three-dimensional (3D) transistor includes a ferroelectric film between the gate and the channel. The 3D transistor can be characterized as a 3D Negative Capacitance (NC) transistor due to the negative capacitance resulting from the ferroelectric film. Performance of the transistor is optimized by manipulating the structure and/or by the selection of materials. In one example, the capacitance of the ferroelectric film (C FE ) is matched to the sum of the gate capacitance (C MOS ) and the gate edge capacitance (C EDGE ), wherein the gate edge capacitance (C EDGE ) is the capacitance at the edge of the gate and between the gate and the source and its extension, and the gate and the drain and its extension.

High-resolution power electronics measurements

Abstract: Disclosed examples include systems to determine an on-state impedance of a high voltage transistor, and measurement circuits to measure the drain voltage of a drain terminal of the high voltage transistor during switching, including an attenuator circuit to generate an attenuator output signal representing a voltage across the high voltage transistor when the high voltage transistor is turned on, and a differential amplifier to provide an amplified sense voltage signal according to the attenuator output signal. The attenuator circuit includes a clamp transistor coupled with the drain terminal of the high voltage transistor to provide a sense signal to a first internal node, a resistive voltage divider circuit to provide the attenuator output signal based on the sense signal, and a first clamp circuit to limit the sense signal voltage when the high voltage transistor is turned off.

Physics understanding of high temperature behavior of Gallium Nitride power transistor

Abstract: This paper presents static and dynamic characterization of 100V and 650V Gallium Nitride power transistor from root temperature to 150°C, and a physical explanation of the device on-resistance behavior at elevated temperature was provided. This device physics-based understanding would benefit those application engineers who selects GaN HEMT power transistor to design a robust and energy efficient power electronic system, considering the device degradation in high temperature ambient.

The next high-performance transistor [News]

Abstract: Five years ago, Intel introduced today's high-performance transistor to the world. Dubbed the FinFET, the device takes its name from its appearance: The transistor's current-carrying channel sticks up vertically in the shape of a fin, and the gate that controls it drapes over the sides. The result is a much tighter control over the flow of current, which in modern microprocessors can fairly easily sneak across the transistor when it's supposed to be shut off. But well before the FinFET exploded onto the scene in 2011, engineers and device physicists had already been looking at the possibility of taking that transistor geometry to its logical conclusion, with a gate that completely surrounds the current- carrying channel. Shifting to such a "gate-all-around" geometry would, in theory, allow chip companies to produce shorter transistors that don't leak copious amounts of current, improving speed or power consumption in the process.

Single-input GaN gate driver based on depletion-mode logic integrated with a 600 V GaN-on-Si power transistor

Abstract: This work presents a monolithically-integrated power circuit with a single control input gate driver based on depletion-mode logic and a 600 V, 150 mΩ power HEMT in GaN-on-Si technology. The gate driver final-stage is a push-pull circuit, in which the pull-up transistor is indirectly driven through a depletion-load logic inverter, whereas the pull-down transistor is directly driven by the single external control input. Measurements of soft- and hard-switching turn-on transitions in an inductive-load half-bridge at 300 V/ 4 A demonstrate controllability of the turn-on speed by adding an external speedup resistor in parallel to the depletion-load. Gate-charge measurements show a 25-fold reduction of external pre-driver drive capability requirement during a 400 V turn-on transition, since the main power transistor gate-charge (8.5 nC)-related losses are provided and dissipated within the GaN power device, and only the pull-down gate driver transistor gate-charge of 0.34 nC has to be provided externally by the pre-driver circuit.

Reduced Local Threshold Voltage Variation MOSFET Using Multiple Layers of Epi for Improved Device Operation

Abstract: A device structure with multiple layers of low temperature epitaxy is disclosed that eliminates source and drain and extension implants, providing a planar interface with abrupt junctions between epitaxial extensions and substrate, mitigating electrostatic coupling between transistor drain and transistor channel and reducing short channel effects The reduction of channel doping results in improved device performance from reduced impurity scattering and reduction of random dopant induced threshold voltage variations (sigma-Vt) Avoiding implants further reduces device sigma-Vt due to random dopants' diffusion from source and drain extensions, which creates device channel length variations during thermal activation anneal of implanted dopants The defined transistor structure employs at least two levels of low-temperature epitaxy, and creates a planar interface with various types of transistor substrates resulting in performance improvement Mixed epitaxial layer growth materials inducing tensile or compressive gate stresses can be advantageously used with the invention to further improve device characteristics

Static random access memory (sram) device for improving electrical characteristics and logic device including the same

Abstract: A static random access memory (SRAM) device includes a circuit element that includes a first inverter having a first load transistor and a first drive transistor and a second inverter having a second load transistor and a second drive transistor. Input and output nodes of the first inverter and the second inverter are cross-connected to each other. A first transfer transistor is connected to the output node of the first inverter, and a second transfer transistor is connected to the output nodes of the second inverter. Each of the first and second load transistors, the first and second drive transistors, and the first and second transfer transistors includes a transistor having multi-bridge channels. At least one of the first and second load transistors, the first and second drive transistors, and the first and second transfer transistors includes a transistor having a different number of multi-bridge channels from the other transistors.

Transistor testing circuit and method thereof, semiconductor memory apparatus and semiconductor apparatus

Abstract: A transistor testing circuit for measuring a breakdown voltage of a transistor included in a semiconductor apparatus with high accuracy for each chip is provided. The transistor testing circuit is disposed on a semiconductor chip to measure the breakdown voltage of a MOS transistor. The transistor testing circuit includes: a voltage applying apparatus, a current detecting circuit, a current mirror voltage outputting circuit, and a comparator circuit. The voltage applying apparatus applies a predetermined testing voltage to at least one of a drain, a source, and a gate of the MOS transistor. When the testing voltage is applied, the current detecting circuit detects a current flowing from the MOS transistor to a load circuit. The current mirror voltage outputting circuit generates a mirror current corresponding to the detected current and outputs the same. The comparator circuit compares the mirror current with a predetermined reference current to output a comparison result signal.

Three-Port Model of a Modern MOS Transistor in Millimeter Wave Band, Considering Distributed Effects

Abstract: Distributed nature of an MOS transistor becomes significant in high frequencies, especially in the millimeter wave band. Two types of distributed effects are encountered in an MOS transistor: the distributed effect along the transistor channel, referred as nonquasi static (NQS) effect, and the distributed effect along the gate finger. We denote the former as lateral distributed effect and the later as longitudinal distributed effect (LDE). Lateral distributed effect has been studied in many works and has been considered either accurately or approximately in the available MOS small-signal models. However, LDEs have not accurately been accounted for, except for few works in which an MOS transistor has been analyzed using transmission line approach to derive two-port ${Y}$ parameters of the transistor. Unfortunately, the two-port distributed model is not useful when the transistor is used in common gate, common drain, or cascode configurations. In this paper, we have developed a new three-port distributed model of an MOS transistor to accurately capture the LDEs. Furthermore, the proposed model can be used in conjunction with new Berkeley short-channel IGFET model (BSIM) radio frequency (RF) small-signal models, such as BSIM4.7 and BSIM6. To evaluate the proposed model, we have used Taiwan Semiconductor Manufacturing Company 90 nm RF-CMOS technology parameters. Our results show that LDE is considerably more significant than NQS effect in millimeter wave band, in the case of a short channel MOS transistor with long gate finger. This reveals the importance of LDEs in RF MOS transistor models, especially in millimeter wave band applications.

Cmos image sensor with enhanced dynamic range

Abstract: An image sensor includes a semiconductor substrate having a main surface, a transfer transistor having a transfer gate disposed on the main surface, a light-sensing structure on one side of the transfer gate, a floating diffusion node on the other side of the transfer gate, a reset transistor serially connected to the transfer transistor via the floating diffusion node, a source-follower transistor having a source-follower gate, and a vertical capacitor having a first vertical electrode plate and a second vertical electrode plate. The first vertical electrode plate is electrically connected to the source-follower gate and the floating diffusion node.

Method and System for Increasing Efficiency and Controlling Slew Rate in DC-DC Converters

Abstract: One embodiment pertains to a method including transitioning a logic state of at least one enable signal. A first power transistor begins to turn off. A parameter level of the input of the first power transistor is directly sensed. A second power transistor is turned off when the parameter level is less than a threshold level.

Driver for a power field-effect transistor, related system and integrated circuit

Abstract: A driver for a power field-effect transistor includes a first and second circuits that apply respective charge currents to a gate of the power field-effect transistor when a control signal has a first logic value and the voltage between the gate and the source is smaller than a first threshold voltage and greater than a second threshold voltage. Third and fourth circuits apply respective discharge currents to the gate when the control signal has a second logic value and the voltage between the gate and the source is greater than a third threshold voltage and smaller than a fourth threshold voltage. The driver may include at least one field-effect transistor configured to generate at least one of the first, second, third or fourth threshold voltage.

Charge pump circuit capable of reducing reverse currents

Abstract: A charge pump unit capable of reducing reverse current includes a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, and a second PMOS transistor. The first NMOS transistor and the first PMOS transistor are coupled in series and are controlled by a first clock signal. The second NMOS transistor and the second PMOS transistor are coupled in series and are controlled by a second clock signal. The first NMOS transistor is for receiving a first input voltage and the second NMOS transistor is for receiving a second input voltage. The first clock signal and the second clock signal transit at different time points. A rising edge of the first clock signal leads a respective falling edge of the second clock signal.

Fast transient low drop-out voltage regulator for a voltage-mode driver

Abstract: An example voltage regulator includes an output transistor that includes a source coupled to a first voltage supply node and a drain coupled to an output node. The voltage regulator further includes a first transistor that includes a source coupled to the output node, and a second transistor that includes a source coupled to a gate of the output transistor and a drain coupled to a second voltage supply node. The voltage regulator further includes a resistor coupled between the second voltage supply node and a first node that includes the drain of the first transistor and a gate of the second transistor. The voltage regulator further includes an error amplifier that includes a first input coupled to a reference voltage node, a second input coupled to the output node, and an output coupled to a gate of the first transistor.

Power Converter with Low Threshold Voltage Transistor

Abstract: A power converter with a high side transistor and a low side transistor produces a phase voltage as the high and low side transistors turn on and off under control of a high side driver and a low side driver, respectively. The low side transistor has a low threshold voltage of 0.4 volts or less. In some embodiments, a drive voltage less than 0 volts turns off the low side transistor. In some embodiments, a low impedance between the low side driver and the low side transistor enables the drive voltage to turn off the low side transistor during high output transients. In some embodiments, the high side transistor, the low side transistor, the high side driver, and the low side driver are integrated together on the same integrated circuit die.

Driver circuit charging charge node

Abstract: Disclosed is a driver circuit The driver circuit includes a clamp transistor, a comparison voltage transistor, an amplification transistor, a bias transistor, and a charge circuit The comparison voltage is configured to provide a comparison voltage The amplification transistor includes an amplification gate connected to a first node of the clamp transistor, a first amplification node configured to receive the comparison voltage, and a second amplification node connected to a gate of the clamp transistor The bias transistor is configured to supply a bias voltage The charge circuit is at least one of configured to drain a current from the first node through the clamp transistor and configured to supply a current to the first node through the clamp transistor

Semiconductor device, memory device, electronic device, and method for operating the semiconductor device

Abstract: A semiconductor device or a memory device with a reduced area, a large storage capacity, a high-speed operation, or low power consumption is provided. The semiconductor device includes a first transistor, a second transistor, a capacitor, a first wiring, a second wiring, a sense amplifier circuit, a decoder, a step-up circuit, a level shifter, and a buffer circuit. The first wiring is electrically connected to the buffer circuit and a second gate electrode of the first transistor. The second wiring is electrically connected to the sense amplifier circuit and the drain electrode of the second transistor. The capacitor is electrically connected to the drain electrode of the first transistor and the source electrode of the second transistor.