Showing papers on "Static induction transistor published in 2017"

Normally OFF Trench CAVET With Active Mg-Doped GaN as Current Blocking Layer

Abstract: A normally OFF trench current aperture vertical electron transistor (CAVET) was designed and successfully fabricated with Mg-doped p-GaN current blocking layers. The buried Mg-doped GaN was activated using a postregrowth annealing process. The source-to-drain body diode showed an excellent p-n junction characteristics, blocking over 1 kV, sustaining a maximum blocking electric field of 3.8 MV/cm. Three-terminal breakdown voltages of trench-CAVETs, measured up to 225 V, were limited by dielectric breakdown. This paper highlights the achievement of the well-behaved buried p-n junction that has been a formidable challenge in the success of vertical GaN devices.

Power loss of GaN transistor reverse diodes in a high frequency high voltage resonant rectifier

Abstract: This paper presents power loss measurements of GaN transistor reverse diodes in high frequency high voltage conditions To evaluate their performance, we use GaN transistor reverse diodes as rectifying devices in a class-DE resonant rectifier and operate the circuit at switching frequencies of 10s of MHz and with output voltages reaching 100s of volts We use a thermometric calibration method to quantify the power loss in all GaN transistor reverse diodes and finds that the losses increase with both switching frequency and output voltage Further, our experiments show that the device power loss is neither hard switching loss by a faulty design of resonant rectifiers nor traditional conduction loss from the forward voltage drop and static on-resistance of the diode The comparison between power dissipation and GaN transistor output capacitances suggests that the device capacitance might be correlated with the observed device power loss

Demonstration of GaN Static Induction Transistor (SIT) Using Self-Aligned Process

Abstract: The rapid development of RF power electronics requires amplifier operating at high frequency with high output power. GaN-based HEMTs as RF devices have made continuous progress in the last two decades showing great potential for working up to G band range. However, vertical structure is preferred to obtain higher output power. In this paper, we have designed and fabricated GaN static induction transistor using the self-aligned technology, which was accomplished mainly by using a SiO2 lift-off step in buffered oxide etch (BOE). By optimizing the time in ultrasonic bath and in BOE, the SiO2 and the metal on top were removed completely which resulted in the gate metal only on the sidewalls. Both dry and wet etch techniques were investigated to reduce the gate leakage on the etched surface. The low power dry etch combined with the tetramethylammonium hydroxide wet etch can effectively reduce the etch damages, decrease the gate leakage and enhance the gate control over the channel.

Static random access memory (sram) cells including vertical channel transistors and methods of forming the same

Abstract: A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor.

Wireless power transfer control apparatus and method

Abstract: An apparatus comprises a sense transistor having a gate and a source directly connected to a gate and a source of a power transistor of a resonant converter respectively, wherein the resonant converter comprises a primary side and a secondary side magnetically coupled to the primary side, a current sense and amplification circuit comprising an amplifier having inputs connected to a drain of the sense transistor and a drain of the power transistor respectively, an analog-to-digital converter connected to an output of the current sense and amplification circuit and a digital controller connected to an output of the analog-to-digital converter, wherein the digital controller is configured to modulate a variable capacitance network of the resonant converter based upon a current flowing through the sense transistor.

Precise control of vertical transistor gate length

Abstract: Transistor and methods of forming the same include forming a channel fin on a bottom source/drain region. A dielectric fill is formed around the channel fin with a gap in an area directly above the channel fin that has a width greater than a width of the channel fin. Spacers are formed in the gap. The dielectric fill is etched away. A gate stack is formed on sidewalls of the channel fin directly underneath the spacers.

Electric circuit including a semiconductor device with a first transistor, a second transistor and a control circuit

Abstract: An electric circuit includes a semiconductor device. The semiconductor device includes a first transistor and a second transistor in a common semiconductor substrate. The first transistor is of the same conductivity type as the second transistor. A first source region of the first transistor is electrically connected to a first source terminal via a first main surface of the semiconductor substrate. A second drain region of the second transistor is electrically connected to a second drain terminal via a first main surface of the semiconductor substrate. A first drain region of the first transistor and a second source region of the second transistor are electrically connected to an output terminal via a second main surface of the semiconductor substrate. The electric circuit further includes a control circuit operable to control a first gate electrode of the first transistor and a second gate electrode of the second transistor.

Vertical Transistor With n-Bridge and Body on Gate for Low-Power 1T-DRAM Application

Abstract: In this paper, we propose a vertical transistor with n-bridge and body on gate (BOG-DRAM) for Low-power 1T-DRAM application. The vertical channel of the device can reduce the short-channel effect and improve scalability. The storage region stacked on the gate leads to the efficient utilization of storage space. The device with junctionless channel layers on three sides can improve writing time. The conventional current bridge device only has one side gate-control depletion region, but the proposed BOG-DRAM has triple-side gate-control depletion region which can improve programming window at shorter gate lengths. BOG-DRAM achieves programming window of $33.6~\mu \text{A}/\mu \text{m}$ when the storage length is 20 nm. In addition, the work function offset is exploited for low-power application.

Static and dynamic characterization of a GaN-on-GaN 600 V, 2 a vertical transistor

Abstract: Vertical GaN power semiconductors promise higher power with faster switching speeds but the development of this technology has been slowed. This is due to the expense and lack of familiarity with GaN substrates. This paper will detail the functionality of HRL's cutting-edge vertical GaN transistor which is mounted onto a specially made PCB and tested. The testing consists of a static characterization which shows a breakdown voltage of 600 V, as well as the transfer characteristics, output characteristics, and the on-state resistance with respect to current. The device is then switched at various voltages and currents with voltage switching speeds up to 97 V/ns. The device is successfully switched up to 450 V under a 2 A load current.

Impedance control in radio-frequency switches

Abstract: A radio-frequency switch includes a first field-effect transistor disposed between a first node and a second node, the first field-effect transistor having a source, a drain, a gate, and a body. The switch further includes a coupling path connected between the body of the first field-effect transistor and the gate of the first field-effect transistor, the coupling path including a diode. The switch further includes an adjustable impedance network connected between the body of the first field-effect transistor and a ground reference, the adjustable impedance network being configured to reduce radio-frequency distortion in the first field-effect transistor.

Reconfigurable U-Shaped Tunnel Field-Effect Transistor

Abstract: A reconfigurable U-shaped tunnel field-effect transistor (RUTFET) is proposed as a low-power dynamically programmable logic device. It has several advantages over conventional reconfigurable TFETs: 1) Excellent scalability without any degradation of subthreshold swing (SS) and drain-induced barrier thinning (DIBT) with recessed channel structure. 2) High current drivability with increased band-to-band tunneling junction 3) Scaling of SS with tunneling barrier width defined by geometrical parameters. In this manuscript, its electrical characteristics are examined by technology computer-aided design (TCAD) simulation. It shows ~30× higher ON-state current than control devices and 41.8 mV/dec-SS during drain current increase by five orders magnitude. The reconfigurable operations for nand p-type FETs are also discussed.

Field-effect transistor with protection diodes

Abstract: A field-effect transistor with protection diodes includes: a field-effect transistor; and a two-terminal electrostatic protection circuit connected between a gate and a source of the field-effect transistor, wherein the two-terminal electrostatic protection circuit comprises: a first diode that is positioned on a reverse-biased side when a voltage lower than a potential of the source is applied to the gate and has a reverse withstand voltage lower than a reverse withstand voltage between the gate and the source of the field-effect transistor; a second diode that is positioned on a forward-biased side when a voltage lower than a potential of the source is applied to the gate and is connected in anti-series to the first diode; and a resistor that is connected in series to a diode pair comprising the first diode and the second diode and formed using a same channel layer as that of the field-effect transistor.

Semiconductor device for reducing an instantaneous voltage drop

Abstract: A semiconductor device for reducing an instantaneous voltage drop is provided. The semiconductor device includes a first power line configured to provide a first power supply voltage and a first power transistor connected between the first power line and a first logic transistor. The first power transistor includes a first source or drain connected to the first power line, a gate receiving a power gating control signal, and a second source or drain connected to a first source or drain of the first logic transistor using a shared semiconductor junction.

Method and system for reliable bootstrapping switches

Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein: source terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor; drain terminals of both the diode-connected transistor and the second MOS transistor are coupled to a source terminal of a third MOS transistor, the third MOS transistor coupled in series with a fourth MOS transistor; and a drain terminal of the fourth MOS transistor is coupled to ground. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage to activate the pull-down path.

Analysis of breakdown voltage of a field plated High Electron Mobility Transistor

Abstract: This paper proposes a High Electron Mobility Transistor (HEMT) which analyzed using Silvaco ATLASTM Tools. The proposed device is an AlGaN/GaN HEMT with AlN acting as a spacer layer. The design also includes a field plated gate to increase the breakdown voltage (F br ). The proposed device has a low threshold voltage V t =−11 V and minimal OFF state leakage current. The device exhibits peak drain current of 2.5 mA when the gate is biased at V gs = 1 V. The subthreshold slope is observed as 75 mV/dec and the ON-OFF current ratio observed is 1014. The proposed device achieves breakdown voltage in the range of 231 to 235 volts depending upon thickness of Gallium Nitride channel layer and hence the device can find high power applications.

Adjusting drive strength for driving transistor device

Abstract: A system that can include a detector that can monitor a voltage at an input of a transistor device over a period of time and provide a signal having a value representative of a capacitance between the input and an output of the transistor device. The system can further include a driver that can have a programmable drive strength and be coupled to input of the transistor device to drive the transistor device at the input thereof. The system can further include a controller that can configure the driver based on the signal to drive the transistor device with a corresponding drive strength.

A comparison of time-average power losses in insulated-gate bipolar transistors and hybrid SIT–MOS–transistors

Abstract: Switching of equivalent silicon insulated-gate bipolar transistors, such as carrier-stored trenchgate bipolar transistors (CSTBTs) and hybrid static induction transistor/metal–oxide–semiconductor (SIT–MOS) thyristors (HSMTs), from a blocking state to a conducting state and vice versa is numerically simulated in two dimensions. It is shown that on–off switching losses in an HSMT are greater than in a fully equivalent CSTBT. Thus, time-average power P that dissipates in an HSMT becomes smaller than the power in the equivalent CSTBTh only at a long current pulse duration. However, a decrease in lifetime τ0 of nonequilibrium charge carriers in an SIT makes it possible to significantly reduce HSMT switching losses while maintaining its advantage in the on state. Consequently, for each set of CSTBT parameters, such τ0, it can be selected in the almost equivalent HSMT that power P dissipating in the HSMT will be smaller than the power in the equivalent CSTBT in any given range of amplitude J a and duration T on of the current pulses.

Substrate bias effect of epitaxial delta-doped channel MOS transistor for low-power applications

Abstract: Conventional planar transistor shows shrinking substrate bias effect at scaled technology. On the other hand, epitaxial delta-doped channel (EδDC) transistor shows substantial amount of substrate bias effect even at 16-nm channel length. This paper unveils the physics behind the substrate bias effect of an n-channel EδDC transistor through Technology Computer Aided Design simulation with analytical justifications. The depletion width for an EδDC transistor very weakly depends upon the applied substrate bias, and with scaling down of channel length, the depletion width insignificantly gets widened. The substrate control over the channel is high so that significant amount of substrate depletion charge terminates on the gate, instead of on the source and the drain. The degradation of threshold voltage roll off and drain-induced barrier lowering coefficient with the increase of substrate bias, is less for the EδDC transistor, compared to that of a conventional halo free transistor. The dependence of t...

Gate voltage generation circuit, transistor substrate and display device

Abstract: A gate voltage generation circuit generates a gate voltage including a first voltage, a second voltage and a third voltage and supplies the gate voltage to a pixel transistor of a display device. The first voltage is a voltage for opening the pixel transistor. The second voltage is lower than the first voltage and is a voltage for closing the pixel transistor. The third voltage is an intermediate voltage between the first voltage and the second voltage. The voltage rises by way of the intermediate voltage at the time of rising from the second voltage to the first voltage.

Field effect transistor structure

Abstract: A field effect transistor (FET) structure includes a substrate, an internal gate, an insulation layer, a semiconductor strip, a gate dielectric insulator, and a gate conductor. The internal gate includes a floor portion located on the substrate and a wall portion extending from the floor portion. The insulation layer is located on the floor portion of the internal gate. The semiconductor strip is located on the wall portion and a portion of the insulation layer, and the semiconductor strip includes source/drain regions and a channel region adjacent to the source/drain regions. The gate dielectric insulator is located on the channel region. The gate conductor is located on the gate dielectric insulator.

Method, apparatus and system for using tunable timing circuits for fdsoi technology

Abstract: At least one method, apparatus and system disclosed involves providing a design for manufacturing a semiconductor device. An operation modeling of a semiconductor device circuit design is performed. At least one transistor is identified for providing at least one of a first voltage for forward biasing the transistor or a second voltage for reverse biasing the transistor. Selectively providing a delay for adjusting a timing associated with the transistor based upon identifying the at least one transistor for providing the at least one of a first voltage for forward biasing the transistor or a second voltage for reverse biasing.

Method and device for current sensing of small currents

Abstract: A device for current sensing of a power transistor system having a power transistor, a first series circuit which includes a first transistor and a first resistance, the first resistance disposed in a load circuit of the first transistor, a second series circuit which has a second transistor and a second resistance disposed in a load circuit of the second transistor, the first series circuit, the second series circuit and the power transistor situated in parallel with one another, the first resistance connected to the first transistor in an electrically conductive manner when the first transistor is switched on, and the second resistance connected to the second transistor in an electrically conductive manner when the second transistor is switched on, and a gate terminal of the first transistor is connected in an electrically conductive manner to a gate terminal of the power transistor when the power transistor is switched on.

Single poly nonvolatile memory cells

Abstract: A single-poly nonvolatile memory cell includes a coupling capacitor, a cell transistor and a selection transistor. The cell transistor has a floating gate, a first source, and a first drain. The floating gate is coupled to an array control gate/source line through the coupling capacitor. The first source is coupled to the array control gate/source line. The selection transistor has a selection gate, a second source, and a second drain. The selection gate is coupled to a word line. The second source is coupled to the first drain. The second drain is coupled to a bit line.

Gate transistor control circuit

Abstract: A device for controlling a first control gate transistor, including: a second transistor and a third transistor series-connected between a first and a second terminals of application of a power supply voltage, the junction point of these transistors being connected to the gate of the first transistor; a terminal of application of a digital control signal; a circuit for generating an analog signal according to variations of the power supply voltage; and for each of the second and third transistors, a circuit of selection of a control signal of the first transistor representative of said digital signal or of said analog signal.

Transmitter and communication system

Abstract: A transmitter according to the disclosure includes a driver, a first pre-driver, a second pre-driver, and a power-supply-voltage generator. The driver includes a first transistor and a second transistor. The first transistor has a drain supplied with a first power supply voltage, a source led to an output terminal, and a gate. The second transistor has a drain led to the output terminal, a grounded source, and a gate. The first pre-driver is supplied with a second power supply voltage and drives the gate of the first transistor. The second power supply voltage has a positive correlation with the first power supply voltage. The second pre-driver is supplied with a third power supply voltage and drives the gate of the second transistor. The power-supply-voltage generator generates the first power supply voltage, the second power supply voltage, and the third power supply voltage.

Method for programming antifuse-type one time programmable memory cell

Abstract: A method for programming an antifuse-type OTP memory cell is provided. Firstly, a first program voltage is provided to a gate terminal of an antifuse transistor. A first bit line voltage is transmitted to the antifuse transistor. A first voltage stress with a first polarity is provided to a gate oxide layer of the antifuse transistor to form a weak path between the gate terminal and the first drain/source terminal of the antifuse transistor. Secondly, a second program voltage is provided to the gate terminal of the antifuse transistor. A second bit line voltage is transmitted to the antifuse transistor. A second voltage stress with a second polarity is provided to the gate oxide layer of the antifuse transistor. Consequently, a program current is generated along the weak path to rupture the gate oxide layer above the first drain/source terminal.