Showing papers on "Static induction transistor published in 2019"

Prospect of silver nanowire (AgNW) in development of simple and cost-effective vertical organic light-emitting transistors

Abstract: Despite a great potential for low-voltage display applications, vertical organic light-emitting transistors (VOLETs) suffer serious issues of high-cost and complex fabrication techniques, notably for the intermediate electrode. To address this problem, this study demonstrates a cost-effective and simple approach to fabricate a VOLET device by utilising spin-coated silver nanowires (AgNWs) as an intermediate electrode. AgNWs exhibit high electrical conductivity, high porosity and high optical transparency, which qualify them as a perfect candidate for the intermediate electrode in VOLETs. To show the potential of AgNWs in VOLET devices using a facile, cost-effective spin-coated method, two types of VOLETs, namely, the Schottky barrier (SB) VOLET and static induction transistor (SIT) VOLET, were fabricated and analysed. Interestingly, both the devices show transistor behaviour when the Vg is varied, implying a fully functional VOLET device. We believe that this is one of the simplest methods to fabricate VOLETs without compromising the device characteristics demonstrated to date.

Proposal and Realization of Vertical GaN Nanowire Static Induction Transistor

Abstract: Vertical gallium nitride (GaN) nanowire static induction transistors (SITs) are proposed and realized for micro display for the first time. A top-down dry etch was employed to form the GaN nanowires with height of $\sim 1.5~\mu \text{m}$ and diameter of ~350 nm, followed by the SIT fabrication with the gate-all-around design which benefits are better gate control, combined with reduced surface area consumption for improved scaling and integration. Relatively low voltages are required for controlling the vertical current from source to drain. The $\text{I}_{\text {on}}$ to $\text{I}_{\text {off}}$ ratio is measured as ${2}\times {10}^{{6}}$ , which is ~900 times larger than the previous reported GaN fin SIT. These results demonstrated that vertical nanowire SITs by the use of undoped GaN which is typically the template layer for light-emitting diodes (LEDs) will enable voltage-controlled components for new integration schemes and opportunities in micro display technology.

Analysis of Deep Level and Oxide Interface Defects Using 100V HF Schottky Diodes and MOS CV for Silicon and 4H SiC HV MOSFETs, Advanced Power Electronics, and RF ASIC

Abstract: In this paper we report high voltage MOS and Schottky Diode CV techniques for silicon and SiC power devices. 4H Silicon carbide is a wide bandgap semiconductor suitable for high voltage power electronics and RF applications due to high avalanche breakdown critical electric field, and thermal conductivity. The performance of various power devices, which may include MOSFET and Static Induction Transistor (SIT), can be affected by the deep level traps in the substrate and the oxide interfacial defects. We have characterized deep level trap (High Voltage Schottky Diode HF CV) and oxide interface trap densities (High Voltage HF MOS CV), measured the device channel doping profile for both 4H SiC and silicon, gate metal workfunction, and simulated the effects on DC/AC performance.

Stress Test of Cascode Switch Using SiC Static Induction Transistor

Abstract: Stress tests were conducted for the cascode switch using the SiC buried gate static induction transistor (SiC-BGSIT). The stress of the reverse overshoot voltage was periodically applied to the pn junction between the gate terminal and source one in the BGSIT in the cascode with pulses of 40kHz for 202 hours. This simulates the stress which can be occurred in the channel region of the BGSIT during the turn-off and turn-on operation with a parasitic inductance in the interconnection of the cascode package. The result of the stress tests has revealed that there is no significant difference between the electrical characteristics of the BGSIT cascode sample before the stress and those after the stress. Thus, the BGSIT cascode can guarantee high reliability against the stress. The result from the drain current DLTS suggests that no deferent kind of defect is created in the channel region of the BGSIT by the stress.