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Static induction transistor

About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.


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Patent
05 Jan 1999
TL;DR: In this paper, a match line control circuit includes a weak, static pull-up transistor and a strong, dynamic pullup transistor coupled between the match line of an associated CAM and a supply voltage.
Abstract: A match line control circuit includes a weak, static pull-up transistor and a strong, dynamic pull-up transistor coupled between a match line of an associated CAM and a supply voltage. Prior to compare operations, both the static pull-up transistor and the dynamic pull-up transistor are in a conductive state and thereby quickly charge the match line to the supply voltage. During compare operations, the dynamic transistor is turned off to reduce current flow between the supply voltage and the match line. In some embodiments, the static pull-up transistor and the dynamic pull-up transistor are configured to match the parasitics of the CAM cells 10 coupled to the match line, thereby increasing performance of the associated CAM.

39 citations

Patent
28 May 2004
TL;DR: In this paper, a multi-stage amplifier with non-field-plate and field-plate transistors is described. But the authors do not specify the characteristics of the transistors.
Abstract: A multi-stage amplifier circuit arranged to take advantage of the desirable characteristics of non-field-plate and field plate transistors when amplifying a signal. One embodiment of a multi-stage amplifier according to the present invention comprises a non-field-plate transistor and a field-plate transistor. The field-plate transistor has at least one field plate arranged to reduce the electric field strength within the field plate transistor during operation. The non-field plate transistor is connected to the field plate transistor, with the non-field-plate providing current gain and the field plate transistor providing voltage gain. In one embodiment the non-field-plate and field plate transistors are coupled together in a cascode arrangement.

39 citations

Patent
09 Apr 2001
TL;DR: In this article, a low power low noise amplifier is proposed, which achieves a high power gain without increasing power consumption by sharing the bias current by using a cascade structure composed of a parallel connected common source transistor and common gate transistor connected to a common source, an inverter type structure connected to the common source transistors, and structure improving the third-order intermodulation component using the parallel connected Common Source Transistor and Common Gate transistor.
Abstract: A low power low noise amplifier achieves a high power gain without increasing power consumption by sharing the bias current. The amplifier is composed of a cascade structure which consists of a parallel connected common source transistor and common gate transistor connected to a common source transistor, an inverter type structure connected to the common source transistor, and structure improving the third-order intermodulation component using the parallel connected common source transistor and common gate transistor.

39 citations

Patent
Kiyoshi Mori1
19 Feb 1991
TL;DR: The floating-gate transistor as discussed by the authors is a metal-oxide-semiconductor transistor constructed in a trench extending through layers of P-type and N-type material formed on a semiconductor substrate.
Abstract: An electrically erasable, programmable, read-only-memory, floating-gate, metal-oxide-semiconductor transistor constructed in a trench extending through layers of P-type and N-type material formed on a semiconductor substrate. The floating-gate transistor is comprised of two source-drain regions, a channel region, a floating gate, a programming gate, and gate-oxide layers and is characterized by a floating-gate to channel capacitance that is small relative to the programming-gate to floating-gate capacitance, thereby allowing charging of the floating gate using programming and erasing voltages of less magnitude than might otherwise be necessary.

39 citations

Journal ArticleDOI
TL;DR: In this paper, the influence of envirommental impedances on tunneling rates in a single electron transistor circuit is investigated and the effect of the finite gate capacitance and of stray capacitances at the tunnel junctions is considered.
Abstract: The influence of envirommental impedances on tunneling rates in a single electron transistor circuit is investigated. Effects of the finite gate capacitance and of stray capacitances at the tunnel junctions are considered. For the case of a low impedance environment the electron tunneling rates reduce to the so-called global rule rate while for a high impedance environment a modification of the so-called local rule rate arises from the stray capacitances. Special emphasis is given to the dependence of the current on the gate voltage which determines the sensitivity of electrometers based on the transistor setup. It is found that a higher sensitivity of the electrometer can be achieved by means of asymmetric transistors.

39 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20234
20225
20211
20203
20196
20189