Static induction transistor

About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.

Single-transistor electrically-alterable switch employing fowler nordheim tunneling for program and erase

Abstract: A one-transistor, electrically-alterable switch in combination with a pass transistor includes a first MOS transistor having a drain, a gate, and a source, and a pass transistor having a drain, a source and a floating gate. The floating gate is capacitively coupled to the source of the first MOS transistor through a tunneling dielectric. An erase electrode is capacitively coupled to the floating gate through a coupling dielectric.

Apparatus and method for protection of electronic circuits operating under high stress conditions

Abstract: Apparatus and methods for electronic circuit protection under high stress operating conditions are provided. In one embodiment, an apparatus includes a substrate (47) having a first p-well (44c), a second p-well (44b) adjacent the first p-well, and an n-type region (46) separating the first and second p- wells. An n-type active area (43b) is over the first p-well and a p-type active area (42b) is over the second p-well. The n-type and p-type active areas are electrically connected to a cathode and anode of a high reverse blocking voltage (HRBV) device (40), respectively. The n-type active area, the first p- well and the n-type region operate as an NPN bipolar transistor (58a) and the second p- well, the n-type region, and the first p-well operate as a PNP bipolar transistor (53a). The NPN bipolar transistor defines a relatively low forward trigger voltage of the HRBV device and the PNP bipolar transistor defines a relatively high reverse breakdown voltage of the HRBV device.

Load actuation circuit

Abstract: An output MOS transistor (2) and a current-detecting MOS transistor (3) are connected commonly at their drains and gates. A gate voltage is fed to the gates of these transistors via signal lines (L1, L2). When the voltage of an output terminal (10) is increased in response to excessive load current, a current-mirror circuit (100) consisting of first and second transistors (4, 5) pulls in current from the signal line (L2) to reduce the gate voltage. Thus, the output current (I1) of output MOS transistor (2) is limited within a predetermined level. Furthermore, a diode (8), provided in the signal line (L2), produces a voltage drop equivalent to the base-emitter voltage of first transistor (4). By the function of this diode (8), the gate-source voltage of output MOS transistor (2) is equalized with the gate-source voltage of current-detecting MOS transistor (3). As a result, the same operating point can be set for the output transistor (2) and the current-detecting transistor (3).

Semiconductor image sensors

Abstract: This invention relates to a semiconductor image sensors and more particularly, to a back-illuminated-type static induction transistor image sensors. FIGS. 4A to 4C show the back illuminated type SIT image sensors operating in the electron depletion storing mode, where the n + buried floating region 23 serves as storage region.

Transistor with overlapping gate/drain and two-layered gate structures

Abstract: Herein disclosed is a semiconductor device of high density. The semiconductor device having a high density and a microstructure is required to have a high breakdown voltage and a high speed even with a low supply voltage. The semiconductor device comprises: a semiconductor body; a gate insulating film formed over the body; and a MOS transistor having a source/drain region formed in the body and a gate electrode film formed over the gate insulating film. The gate electrode film is composed of two or more films having different etching rates. The gate etching is stopped at the interface of the composite film to form an inverse-T gate electrode structure; and in that an electric conduction is observed between the component films. Thus, the overlap between the gate and the drain can be controlled.