Static induction transistor

About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.

Radio frequency power amplifier

Abstract: The present invention relates to a cascode radio frequency power amplifier, including at least two cascaded MOS transistors formed in a mutual substrate, where the bulk nodes of the transistors are isolated from each other and connected to the respective source of each transistor. The present invention also teaches that the drain of the topmost transistor is connected to the power supply through an inductive load, and that the gate of each upper transistor is equipped with a self-biasing circuit connected at least between the drain and the gate of the respective upper transistor.

Static induction transistors optimized for high-voltage operation and high microwave power output

Abstract: An optimized static induction transistor (SIT) design utilizing local oxidation in a self-aligned geometry is described. Devices with 10.5- and 7-µm pitch (gate-to-gate spacing), which have been optimized with respect to epitaxial layer thickness and resistivity, have attained a combination of operating frequency and breakdown voltage which is much higher than devices made with other technologies. The 10.5-µm pitch SIT's have a blocking voltage of 170 V with 6-dB gain at 225 MHz and 10-dB gain at 900 MHz. Typical multicell power devices have demonstrated 110-W output power at 225 MHz with 65-percent drain efficiency and 25 W at 900 MHz with 40-percent drain efficiency, operated at voltages in excess of 100 V de bias. The 7-µm pitch SIT's have a blocking voltage of 140 V and the same power gain performance at 225 and 900 MHz as the 10.5-µm pitch devices, but with higher effiency and a higher maximum frequency of operation. Typical multicell power devices of this type have achieve 110-W output power at 225 MHz with 70-percent drain efficiency and 25 W at 900 MHz with 55-percent drain efficiency operated at 90 V de bias.

High-swing cascode current mirror

Abstract: A high-swing current mirror includes a cascode current source and a current source bias circuit. The current source includes first and second bias terminals and an output terminal. The bias circuit includes transistors M1, M2A, M2B and M3A. Transistor M1 has a gate, source, and drain, with the gate coupled to the drain. Transistor M2A has a gate, source, and drain, with the gate and source of transistor M2A coupled to the gate and source, respectively, of transistor M1. Transistor M2B has a gate and drain coupled to one another and to the second bias terminal and a source coupled to the drain of transistor M2A. Transistor M3A has a gate and drain coupled together and to the first bias terminal and a source coupled to the sources of transistors M1 and M2A. The transistors in the cascode current source and current source bias circuit have ratios of device transconductance parameters such that the cascode current source remains in saturation to provide the highest possible voltage swing at the output terminal.

Composite transistor device with over current protection

Abstract: The base-emitter junctions of a power transistor and an auxiliary transistor are paralleled. The smaller collector current of the auxiliary transistor can be sampled so as to indirectly sample the larger collector current of the power transistor. When the indirect sampling indicates that the collector current in the power transistor is tending to exceed its rated maximum value, its base and emitter electrodes are clamped. This prevents increase in the base-emitter potential of the power transistor and consequently increase of its collectorto-emitter current.

Single-ended and differential transistor amplifier circuits with full signal modulation compensation techniques which are technology independent

Abstract: A compensating transistor (Q5) is connected in series with the collector of a main transistor (Q3), and a level shifted replica (Vin + V1) of an input signal (Vin) is applied to the base of the compensating transistor (Q5) to maintain a constant voltage difference between the base and collector of the main transistor (Q3) and compensate for base width modulation ΔVce. A voltage-controlled current source (S1) is responsive to the input signal (Vin) and applies a compensating current ΔIload which is equal and opposite to the load current variation caused by a change (ΔVin) in the input voltage (Vin) to the emitter of the main transistor (Q3) to compensate for load current modulation ΔVbe. Alternatively, the compensating current can be applied to the junction of the base of the main transistor (Q3) and the emitter of pre-distortion transistor (Q4) which has a base connected to receive the input signal (Vin). Another compensating transistor (Q12) applies a current (ΔIb) which is equal and opposite to a non-linear base current variation to the emitter or collector of the main transistor (Q3) to compensate for current gain modulation ΔIb. The modulation compensation arrangements are applicable to common-collector, common-base and common emitter amplifiers in single-ended and differential configurations, and to substantially all bipolar and field-effect transistor technologies.