Static induction transistor

About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.

Simulation of the amorphous silicon static induction transistor

Abstract: The I – V characteristics of the hydrogenated amorphous silicon Static Induction Transistor are obtained by performing a simulation in two dimensions considering electrons and holes together for the first time. The results show that the device has basically four modes of operation that we identify and interpret physically: saturation, channel opening, ohmic and drain current inversion. The study of the influence of the electron concentration at the ohmic contacts, the channel width and the deep level density of states on the switching properties of the device is undertaken. Besides, we show that the on-current is controlled by the electron concentration at the ohmic contacts whereas the off-current is controlled by the electron concentration at the Schottky contact. Finally, we show that the turn-off voltage increases when the channel width or the deep level density of states increase.

Differential oscillator circuit including an electro-mechanical resonator

Abstract: A differential oscillator circuit including first ( 10 ) and second ( 20 ) branches each including the series arrangement, between high (VDD) and low (VSS) supply potentials, of a transistor ( 4, 5 ) and bias means ( 2, 3, 8, 9 ) for imposing a determined current through the current terminals of the transistor. The transistors are interconnected so as to form a crossed pair of transistors, the most positive current terminal of each transistor (on the “drain” side) being connected to the control terminal of the other transistor of the crossed pair. This differential oscillator circuit further includes an electro-mechanical resonator ( 6 ) connected to the crossed transistor pair on the “drain” side, as well as a capacitive element ( 7 ) connected to the crossed transistor pair on the “source” side. The capacitance value of the capacitive element is selected so as to be less than a maximum value above which relaxation of the oscillator circuit can occur and thereby prevent relaxation of the oscillator circuit.

Negative voltage generator for flash EPROM design

Abstract: A circuit is provided for supplying a negative high voltage to an integrated circuit from a high positive voltage source Vpp. The negative voltage is applied to a plurality of FLASH electrically erasable programmable read only memory (EPROM) cells. The circuit includes an oscillator coupled to a voltage converter which provides a periodic signal. The periodic signal is coupled to a charge pump (3) including three P-channel type transistors to produced the negative voltage. The source and drain of the first transistor (41) is coupled to the periodic signal. The second transistor's (43) gate and drain is coupled to a reference ground potential with the source coupled to the first transistor's gate. Finally, the third transistor's drain and gate is coupled to the first transistor's gate and the third transistor's source outputs negative voltage to floating gates of the plurality of FLASH EPROM cells during an erase operation. Further, the negative voltage generated is relatively precise, so no regulation is required.

Method of making a trench DRAM cell with dynamic gain

Abstract: A two transistor gain-type DRAM cell (8) is formed in a trench (30) to optimize wafer area requirements. Formed on a heavily doped semiconductor substrate (20) are alternate layers of P-type and N-type semiconductor material defining the elements of a vertical pass transistor (12) and gain transistor (24). A trench is formed through the alternate semiconductor layers into the substrate (20), and filled with two regions of a semiconductor material defining a storage node (18) and, insulated therefrom, a word line (16). The gain transistor (24) is fabricated having a response time faster than that of the pass transistor (12) so that, during read operations, the gain transistor (24) changes the precharged voltage of the read bit line (26), depending upon the charge stored in the capacitor storage node (18).

Methods of forming field effect transistors and field effect transistor circuitry

Abstract: Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and connected between the transistor's gate and the body. A second resistive element is received by the substrate and connected between the body and a reference voltage node. The first and second resistive elements form a voltage divider which is configured to selectively change threshold voltages of the field effect transistor with state changes in the gate voltage. In a preferred embodiment, first and second diode assemblies are positioned over the substrate and connected between the gate and body, and the body and a reference voltage node to provide the voltage divider.