Topic
Static induction transistor
About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.
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12 Jul 2004
TL;DR: In this paper, a transistor device comprising source and drain regions (S, D), a nanotube structure (2, 3) providing a path for electrical charge carriers between the source and Drain regions, and a gate region (4).
Abstract: A transistor device comprising source and drain regions (S, D), a nanotube structure (2, 3) providing a path for electrical charge carriers between the source and drain regions, and a gate region (4). The nanotube structure has its conduction band structure locally modified in the gate region, e.g. by doping, for controlling the passage of the charge carriers in the path. The device can be used as a flash memory or as a memory element in a DRAM.
37 citations
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05 Nov 2001TL;DR: In this article, a Faraday shield layer is provided between at least a first portion of the gate electrode and a drain of the field effect transistor in order to capacitively decouple the first portion from the drain.
Abstract: Integrated power devices include a plurality of field effect transistor unit cells and a Faraday shield layer that reduces parasitic gate-to-drain capacitance (Cgd) and concomitantly improves high frequency switching performance. These power devices may include a field effect transistor in an active portion of a semiconductor substrate and a gate electrode that is electrically connected to a gate of the field effect transistor. A Faraday shield layer is provided between at least a first portion of the gate electrode and a drain of the field effect transistor in order to capacitively decouple the first portion of the gate electrode from the drain. The gate electrode and drain typically extend adjacent opposing faces of the semiconductor substrate. The Faraday shield layer is preferably electrically connected to a source of the field effect transistor and provides edge termination.
37 citations
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03 Jun 2009
TL;DR: In this paper, a shift register with a plurality of flip-flop circuits is described. But the flip-FLOP circuit is not considered in this paper, and the potential of a node A is set, so that A is prevented from entering a floating state.
Abstract: To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.
37 citations
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24 Feb 2004TL;DR: In this paper, a high voltage LDMOS transistor with a P-field and divided P-fields in an extended drain region of a N-well is presented. But, the Pfield is not used in this paper.
Abstract: A high voltage LDMOS transistor according to the present invention includes a P-field and divided P-fields in an extended drain region of a N-well. The P-field and divided P-fields form junction-fields in the N-well, in which a drift region is fully depleted before breakdown occurs. Therefore, a higher breakdown voltage is achieved and a higher doping density of the N-well is allowed. Higher doping density can effectively reduce the on-resistance of the LDMOS transistor. Furthermore, the N-well generated beneath a source diffusion region provides a low-impedance path for a source region, which restrict the transistor current flow in between a drain region and a source region.
37 citations
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01 Jan 1985TL;DR: In this paper, specific on-resistance characteristics of the lateral and vertical DMOS transistors are compared for voltages between 50 and 800 volts, and the results indicate that the vertical device has lower specific onresistance at low voltages because of its higher channel width/unit chip area packing.
Abstract: The specific on-resistance characteristics of the lateral and vertical DMOS transistors are compared for voltages between 50 and 800 volts. The vertical DMOS transistor's breakdown and on-resistance relationship is reviewed, followed by modeling results of the lateral DMOS transistor's breakdown and on-resistance characteristics. A direct comparison is then made between the vertical and lateral devices. The results indicate that the vertical device has lower specific on-resistance at low voltages because of its higher channel width/unit chip area packing. At higher voltages, the lateral device becomes equal to or better than the vertical device because of its ability to maintain a high drift region conductivity.
37 citations