Static induction transistor

About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.

Effective base resistance of bipolar transistors

Abstract: Two formulations, one appropriate for dc analysis and the other for low-frequency ac analysis, are developed to calculate effective lumped base resistance of bipolar junction transistors. These formulations are defined in terms of terminal characteristics, and are more appropriate for device behavior in circuit modeling applications than those formulations currently in the literature. This is most apparent at high current levels, where appreciable current crowding is present and all of the models under consideration give markedly different results. The present calculations are made for a discrete transistor of single base-stripe geometry, but the results are applicable to integrated-circuit transistors and can be readily extended to other geometries.

Driver circuit, display device including the driver circuit, and electronic device including the display device

Abstract: One object is, when a thin film transistor whose channel is formed using an amorphous semiconductor is used for a driver circuit formed using only n-channel transistors or p-channel transistors, to provide a driver circuit in which the threshold voltage is compensated in accordance with the degree of change in the threshold voltage. In the driver circuit which includes a unipolar transistor including a first gate and a second gate which are disposed above and below a semiconductor layer with insulating layers provided therebetween, a first signal for controlling switching of the transistor is inputted to the first gate, a second signal for controlling a threshold voltage of the transistor is inputted to the second gate, and the second signal is controlled in accordance with a value of current consumption including a current which flows between a source and a drain of the transistor.

Voltage regulator circuit

Abstract: A voltage regulator circuit includes a transistor and a capacitor. The transistor includes a gate, a source, and a drain, a first signal is inputted to one of the source and the drain, a second signal which is a clock signal is inputted to the gate, an oxide semiconductor layer is used for a channel formation layer, and an off-state current is less than or equal to 10 aA/μm. The capacitor includes a first electrode and a second electrode, the first electrode is electrically connected to the other of the source and the drain of the transistor, and a high power source voltage and a low power source voltage are alternately applied to the second electrode.

High efficiency push-pull inverters

Abstract: High efficiency push-pull inverters minimize undesirable energy losses usually resulting from simultaneous conduction and imperfect switching of the transistor switching means In each of the disclosed circuits, a saturable inductor and a diode are connected in parallel and across the base-emitter junction of each transistor Voltage on the base of each transistor causes its associated saturable inductor to saturate, and the saturated inductor then terminates the flow of base current and provides a path for rapid evacuation of the charge carriers stored in the transistor base-emitter junction in order to render the transistor rapidly non-conductive Each diode provides a drain path for current continuing to flow through its associated saturable inductor after junction evacuation A novel triggering means initiates oscillation of the inverters Also disclosed are feedback means operable to prevent premature transistor conduction and a capacitor connected between the collectors of the inverter transistors operable to restrain the rate of change of transistor collector voltage, both of these features also serving to minimize energy dissipation Iadd

Test apparatus for static-type semiconductor memory devices

Abstract: A static type semiconductor memory device is provided with a power circuit for a disturb test, in which MOS transistors constituting a memory cell are examined for an abnormal threshold voltage. A P-channel MOS transistor is provided between a power supply, and the memory cells. The P-channel MOS transistor is rendered conductive in the normal mode, allowing the voltage to the memory cells as under normal circumstances. In addition, between the power supply and the memory cells, there is provided a series-connection of a diode-connected N-channel MOS transistor and a P-channel MOS transistor. In the disturb test, this P-channel MOS transistor is rendered conductive. As a result, the supply voltage reduced by the N-channel MOS transistor, or a voltage lower than the supply voltage by the threshold voltage of this N-channel MOS transistor is supplied to the memory cells. By configuring the static type semiconductor memory device in this manner, the time required for the potential difference between the two storage nodes in a memory cell to become small enough, due to a defective transistor in the memory cell, to cause malfunction of the device is reduced. Thus, the time required for the disturb test is shortened.