Topic
Static induction transistor
About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.
Papers published on a yearly basis
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06 Jun 2005TL;DR: By modifying the intrinsic stress of a dielectric layer laterally enclosing gate electrode structures of a transistor configuration formed in accordance with in-laid gate techniques, the charge carrier mobility of different transistor elements may individually be adjusted as mentioned in this paper.
Abstract: By locally modifying the intrinsic stress of a dielectric layer laterally enclosing gate electrode structures of a transistor configuration formed in accordance with in-laid gate techniques, the charge carrier mobility of different transistor elements may individually be adjusted. In particular, in in-laid gate structure transistor architecture, NMOS transistors and PMOS transistors may receive a tensile and a compressive stress, respectively.
36 citations
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10 Nov 2000
TL;DR: In this paper, a lateral high voltage transistor device is disclosed, which includes a gate, a drain, and a source, and the drain is located apart from the gate to form an intermediate drift region.
Abstract: A lateral high voltage transistor device is disclosed. The transistor includes a gate, a drain, and a source. The drain is located apart from the gate to form an intermediate drift region. The drift region has variable dopant concentration between the drain and the gate. In addition, a spiral resistor is placed over the drift region and is connected to the drain and either the gate or the source of the transistor.
36 citations
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10 Mar 2008TL;DR: In this article, a method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable nonvolatile memory cells, each having a programming transistor, a read transistor and a control capacitor, which share a common floating gate electrode.
Abstract: A method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable non-volatile memory cells, each having a programming transistor, a read transistor and a control capacitor, which share a common floating gate electrode. The under-diffusion of the source/drain regions of the programming transistor and control capacitor are maximized. In one embodiment, the source/drain regions of the programming transistor are electrically shored by transistor punch-through (or direct contact).
36 citations
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21 May 1996
TL;DR: A power semiconductor structure (200), in particular in VIPower technology, made from a chip of N-type semiconductor material (110), comprising a bipolar or field-effect vertical power transistor (125, 120, 110) having a collector or drain region in such Ntype material (200) was described in this article.
Abstract: A power semiconductor structure (200), in particular in VIPower technology, made from a chip of N-type semiconductor material (110), comprising a bipolar or field-effect vertical power transistor (125, 120, 110) having a collector or drain region in such N-type material (110); the semiconductor structure comprises a PNP bipolar lateral power transistor (210, 110, 220) having a base region in such N-type material (110) substantially in common with the collector or drain region of the vertical power transistor.
36 citations
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06 Jun 2002TL;DR: In this paper, a T-RAM memory cell includes a temperature compensation device to adjust the gate-to-source voltage of an access transistor for the memory cell as a function of temperature so that the sub-threshold current of the transistor is insensitive to temperature variations.
Abstract: A T-RAM memory cell includes a temperature compensation device to adjust the gate-to-source voltage of an access transistor for the memory cell as a function of temperature so that the sub-threshold current of the transistor is insensitive to temperature variations. As a result, the sub-threshold current can be maintained slightly above the holding current of a thyristor used in the memory cell despite substantial temperature variations. In one embodiment, the temperature compensation device includes a current source directing a fixed current through a diode-connected transistor of the type used as the memory cell access transistor. Temperature induced changes in a reference voltage generated at the junction between the current source and the transistor therefore match the temperature induced changed in the sub-threshold current of the access transistor. As a result, the sub-threshold current of the access transistor can be made insensitive to temperature variations by applying the reference voltage to the gate or source of the access transistor.
35 citations