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Static induction transistor

About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.


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Patent
07 Aug 1995
TL;DR: In this paper, a protection circuit for protecting against electrostatic discharges applied to a bonding pad is connected to ground, which includes a primary transistor for conducting the discharge current to ground and a gate voltage controlling circuit for controlling the gate voltage of the primary transistor.
Abstract: A protection circuit for protecting against electrostatic discharges (ESD) applied to a bonding pad is connected to ground. The ESD is discharged to ground through the protection circuit, which includes a primary transistor for conducting the discharge current to ground and a gate voltage controlling circuit for controlling the gate voltage of the primary transistor. Operation of the protection circuits begins from a low electrostatic voltage, thereby positively enhancing the electrostatic voltage resistance. In particular, when the gate voltage controlling circuit is a secondary transistor, the source terminal of the primary transistor is connected to ground, and the drain terminal is connected to the bonding pad. The source terminal of the secondary transistor is also connected to ground. Its gate terminal and drain terminal are connected to the gate terminal of the primary transistor.

34 citations

Patent
Haruko Inoue1, Yuichi Kitamura1
19 Sep 2000
TL;DR: In this article, a high-voltage MOS transistor with a gate insulating film was designed to maintain a high sustaining breakdown voltage, which is based on the voltage of the source offset region and a voltage of a substrate region.
Abstract: A high-voltage MOS transistor wherein a dopant concentration of a source offset region is set lower than a dopant concentration of a drain offset region whereby a resistance value of the resource region is set independently of a resistance value of the drain region in such a manner as to maintain a high sustaining breakdown voltage of the high-voltage MOS transistor, which is based on a voltage of the source offset region and a voltage of a substrate region directly under a gate insulating film during operation of the high-voltage MOS transistor.

34 citations

Patent
Takumi Kawai1, Akihiko Ono1
23 Mar 2001
TL;DR: In this paper, a constant-current driver circuit for on-off controlling an output current at a high speed is provided, where a bias circuit is connected to the gate of the second MOS transistor to provide a bias voltage.
Abstract: A constant-current driver circuit for on-off controlling an output current at a high speed is provided. The constant-current driver circuit includes a first MOS transistor to which a reference current is provided and a second MOS transistor connected to the first MOS transistor for generating an output current having a predetermined ratio to the reference current. A switch circuit is connected to the second MOS transistor to on-off control the output current in accordance with the input signal. A bias circuit is connected to the gate of the second MOS transistor to provide a bias voltage to the gate of the second MOS transistor so that variation in the gate voltage of the second MOS transistor is suppressed.

34 citations

Patent
David S. P. Ho1, Wee Teck Lee1
08 Jun 2004
TL;DR: In this article, a differential line driver includes a plurality of driver cells, each driver cell includes an input Vip and an input Vin, an output Vop and an output Von, a first PMOS transistor and a first NMOS transistor having gates driven by the input Vop, and a second PMOS transistors having gates driving by the output Vin.
Abstract: A differential line driver includes a plurality of driver cells Control logic outputs positive and negative control signals to the driver cells so as to match a combined output impedance of the driver cells at (Vop, Von) Each driver cell includes an input Vip and an input Vin, an output Vop and an output Von, a first PMOS transistor and a first NMOS transistor having gates driven by the input Vip, and a second PMOS transistor and a second NMOS transistor having gates driven by the input Vin A source of the first PMOS transistor is connected to a source of the second PMOS transistor A source of the first NMOS transistor is connected to a source of the second NMOS transistor First and second resistors are connected in series between the first PMOS transistor and the first NMOS transistor, and connected together at Von Third and fourth resistors are connected in series between the second PMOS transistor and the second NMOS transistor, and connected together at Vop A first output switch is driven by a corresponding positive control signal and connected between a supply voltage and the sources of the first and second PMOS transistors A second output switch driven by a corresponding negative control signal and connected between a ground and the sources of the first and second PMOS transistors

34 citations

Patent
10 Jun 2010
TL;DR: In this article, a high-voltage semiconductor device and a high voltage integrated circuit device are presented, which achieves low voltage driving and quick response by way of stable high voltage wiring and a low ON voltage.
Abstract: Aspects of the present invention provide a high-voltage semiconductor device and a high voltage integrated circuit device while minimizing or eliminating the need for the addition of back surface steps. Aspects of the invention provide a high-voltage semiconductor device that achieves, low voltage driving and quick response by way of stable high voltage wiring and a low ON voltage. In some aspects of the invention, a high-voltage semiconductor device can include a semiconductor layer is formed on a support substrate interposing an embedded oxide film therebetween. A high potential side second stage transistor and a low potential side first stage transistor surrounding the second stage transistor are formed on the surface region of the semiconductor layer. The source electrode of the second stage transistor is connected to the drain electrode of the first stage transistor. A drain electrode of the second stage transistor is connected to a drain pad.

34 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20234
20225
20211
20203
20196
20189