Static induction transistor

About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.

Switch-mode power supply with over-current protection

Abstract: In a tuned switch mode power supply a zero voltage is maintained across a transistor switch (Q3), during both turn off and turn on switching transition intervals in the transistor switch. The tuned switch mode power supply operates in a current-mode control, on a current pulse-by-current pulse control basis. An over-current protection circuit (200) disables the transistor switch when an over-current condition persists longer than a first interval that is substantially longer than a period of a given current pulse in the transistor switch. The operation of the transistor switch is undisturbed, when the over-current condition lasts only a shorter interval than the first interval.

Ultra high density NOR gate using a stacked transistor arrangement

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of a lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor. In addition to the inverted, shared gate conductor, the multi-level transistor fabrication process incorporates formation of openings and filling of those openings to produce interconnect to junctions of the upper/lower transistors. Interconnecting the gate conductors of a pair of stacked transistors and connecting specific junctions of those transistors allow development of a high density NOR gate. The NOR gate includes two pairs of stacked transistors, wherein one transistor of a pair can be connected to the other transistor of that pair or connected to one or both transistors of the other pair.

Charge pump circuit without body effects

Abstract: A charge pump circuit has input and output nodes, a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. A drain of the first transistor and a drain of the second transistor are connected to the input node. A source of the second transistor and a drain of the third transistor are connected to the output node. The first capacitor is connected to a gate of the second transistor. The third transistor is connected to a substrate and a source of the second transistor. When the first transistor is turned on, a voltage at the input node will charge the first capacitor. When the second transistor is turned on, the third transistor is turned on simultaneously so that the substrate and the source of the second transistor will reach the same voltage level. Then, voltage at the input node will charge the second capacitor.

Semiconductor image sensor

Abstract: A semiconductor image sensor which has photocells arranged in a matrix form is miniaturized and integrated with high density, thereby to increase its light amplification factor and operating speed. To this end, each photocell is formed by a static induction transistor which has a pair of main electrodes, a channel region formed between the main electrodes and a capacitor connected between a control region serving as a photocell and one of the row lines.

Multilayered vertical transistor having reach-through isolating contacts

Abstract: Logic circuits for performing the INVERTER and NOR functions, and monolithic integrated structures for realizing the circuits. The basic circuit comprises PNP transistor and an NPN transistor. The emitter of the PNP transistor has its base grounded and its collector connected to the base of the NPN transistor having its emitter grounded. The logic signal input is at the base of the NPN transistor. The output is taken at the collector of the NPN transistor and is the inverse of the input. Two such basic circuits are interconnected to provide the NOR function.