Topic
Static induction transistor
About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.
Papers published on a yearly basis
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22 Jan 1986
TL;DR: In this article, a thermal sensor is formed in close proximity to each output power transistor, and as far away as possible from the other power transistors of the IC, whereby each thermal sensors is thermally, tightly coupled to its associated power transistor.
Abstract: A monolithic integrated circuit (IC) chip in which is formed a multi-driver power circuit, with each driver circuit including one output power transistor, is partitioned such that the power transistor of each driver circuit, formed in the IC, is spaced apart from those of any other driver circuit a distance sufficiently large to ensure the generation of a temperature differential between the power transistors of the different driver circuits when their power dissipation is different. A thermal sensor is formed in close proximity to each output power transistor, and as far away as possible from the other power transistors of the IC, whereby each thermal sensor is thermally, tightly, coupled to its associated power transistor. Each thermal sensor is electrically coupled to the base of its associated power transistor for controlling the conductivity of its associated power transistor when the power dissipation of its associated power transistor and its resulting temperature exceeds a predetermined level.
32 citations
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15 Jan 1999TL;DR: In this paper, a p-channel MOS transistor is formed in the same active region and has its gate electrode connected to the gate electrode of the VDMOS transistor, its source region in common with the source region of the vDMS transistor, and its drain region connected to p-type junction isolation region.
Abstract: The n-channel VDMOS transistor is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed in the same active region and has its gate electrode connected to the gate electrode of the VDMOS transistor, its source region in common with the source region of the VDMOS transistor, and its drain region connected to the p-type junction-isolation region. The p-channel MOS transistor has a threshold voltage below the breakdown voltage of the gate dielectric of the VDMOS transistor so that it acts as a voltage limiter.
32 citations
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26 May 1994TL;DR: In this paper, a zener diode connected from the source to gate of the two field effect transistors is used to provide high voltage protection for a power transistor driving an inductive load.
Abstract: This application discloses circuit and method for reducing the turn-off time of a power transistor driving an inductive load. The circuit clamps the gate to source of a power transistor by using two field effect transistors as the current path across the gate and source of the power transistor. A zener diode connected from the source to gate of the two field effect transistors is used to provide high voltage protection.
32 citations
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22 Dec 1976TL;DR: In this paper, a complementary emitter follower transistor is employed in the biasing of the stacking transistor along with a current source acting as the emitter load, which provides constant current drive for the stack transistor without resorting to low value biasing resistors.
Abstract: In transistor output stages, where the applied voltage exceeds the voltage rating of available transistors, stacking is employed to divide the voltage across two or more series connected devices. A complementary emitter follower transistor is employed in the biasing of the stacking transistor along with a current source acting as the emitter follower load. This arrangement provides constant current drive for the stacking transistor without resorting to low value biasing resistors which produce excessive current flow under quiescent conditions.
32 citations
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25 Jun 2002TL;DR: In this article, the authors proposed a field effect transistor (FE transistor) which has the advantage that a significant increase in the effective channel width for the current flow ION can be guaranteed relative to conventional transistor structures used up to the present.
Abstract: The invention relates to a field effect transistor in which the planar channel region on the upper surface of the elevation is extended in width by means of additional vertical channel regions on the lateral surfaces of the elevation. Said additional vertical channel regions connect directly to the planar channel region (vertical extended channel regions). Said field effect transistor has the advantage that a significant increase in the effective channel width for the current flow ION can be guaranteed relative to conventional transistor structures used up until the present, without having to accept a reduction in the achievable integration density. Said field effect transistor furthermore has a low reverse current IOFF. The above advantages are achieved without the thickness of the gate insulators up to the region of the charge transfer tunnels having to be reduced or a reduced stability.
32 citations