Static induction transistor

About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.

Electrostatic discharge protection circuit for semiconductor device

Abstract: An ESD protection circuit (38) for a MOS device uses at least one electrically floating-base N+P-N+ transistor (43) connected between a metal bonding pad (40) and ground. The electrically floating base region (44) of each transistor is formed by a thin oxide region deposited over a substrate (50) of the MOS device. Because its N+ regions (42, 45) are made symmetrical about the floating base, each transistor conducts ESD pulses of both polarities equally. The beta of each transistor is made sufficiently large to withstand short-duration ESD current spikes. Current density is minimized by diffusing a deep N- well (54, 56) into each N+ region of each transistor to provide a larger effective conducting area. Low capacitance and higher breakdown voltage are achieved by eliminating the gate structure of prior art FET-based protection circuits.

High voltage ESD power clamp

Abstract: Method and device for protecting against electrostatic discharge The method includes configuring a gate of at least one upper transistor of a transistor network connected between power rails to be biased to a prescribed value, and coupling an electrostatic discharge event to a gate of a lower transistor of the transistor network The at least one upper and at least one lower transistors of the transistor network are respectively coupled between the power rails from a higher voltage to a lower voltage

Active pixel sensor with shared readout structure

Abstract: An active pixel sensor with a shared readout structure controls the switching of its transistors in a time-divided manner in conjunction with the appropriate switching of the voltage of a variable voltage source, whereby two pixels in a sensor can share a common readout structure and a selecting transistor commonly used in conventional art is not required. The present invention comprises: a first photodiode and a first NMOS transistor, wherein the anode and cathode of the first photodiode are coupled to a ground and the source of the first NMOS transistor, respectively, and a first selecting signal is coupled to the gate of the first NMOS transistor; a second photodiode and a second NMOS transistor, wherein the anode and cathode of the second photodiode are coupled to the ground and the source of the second NMOS transistor, respectively, and a second selecting signal is coupled to the gate of the second NMOS transistor; and a third NMOS transistor and a fourth NMOS transistor, wherein the drains of the first and second NMOS transistors are coupled to the source of the third NMOS transistor and the gate of the fourth NMOS transistor, and a reset signal is coupled to the gate of the third NMOS transistor, and the drains of the third and fourth NMOS transistors are coupled to a variable voltage source.

High voltage MOS field effect semiconductor device

Abstract: A high voltage MOS field-effect semiconductor device comprising, as formed on a single seimconductor substrate a high voltage first MOS field-effect transistor and a conventional second MOS field-effect transistor operable at a lower voltage than the first transistor. The semiconductor substrate is covered with an aluminum or like conductor layer over the region thereof where the conventional second field-effect transistor is located.

Methods of forming a vertical field-effect transistor and a semiconductor memory cell

Abstract: The disclosure includes a vertical field-effect transistor (115) with a laterally recessed channel region (92), a vertical field-effect transistor (116) having a graded diffusion junction (31), a static random access memory cell (110) having a vertical n-channel field-effect transistor (116) and a vertical p-channel field-effect transistor (115) and methods of forming them. In one embodiment, a six-transistor static random access memory cell (110) has two pass transistors (111 and 114), which are planar n-channel field-effect transistors, two latch transistors (113 and 116), which are vertical n-channel field-effect transistors with drain regions having graded diffusion junctions (31), and two load transistors (112 and 115), which are vertical p-channel thin-film field-effect transistors having laterally recessed channel regions (92).