Static induction transistor

About: Static induction transistor is a research topic. Over the lifetime, 8155 publications have been published within this topic receiving 107058 citations. The topic is also known as: SIT.

Non-volatile memory cells, high voltage transistors and logic transistors integrated on a single chip

Abstract: Semiconductor device having on a single substrate (1) at least one memory cell (3) and at least one logic transistor (25); the at least one memory cell having a floating gate (5), a tunnel oxide layer (11) between the floating gate and the substrate (1), a control gate (15), and a control oxide layer (13) between the control gate (15) and the floating gate (5); the at least one logic transistor (25) having a logic transistor gate (5′, 15″) and a logic transistor gate oxide (11″) between the logic transistor gate (5′, 15″) and the substrate (1), the tunnel oxide layer (11) of the memory cell (3) and the logic transistor gate oxide (11″) having a same or substantially same predetermined first thickness. The invention also relates to a method of manufacturing such a device and to such a device that also comprises a high voltage transistor (17) which is optionally made so as to be an integral part of at least the memory cell (3).

Ultra low power pumped n-channel output buffer with self-bootstrap

Abstract: An ultra-low power pumped n-channel transistor output buffer with self-bootstrapping includes an n-channel pullup transistor as the primary pullup device. A gate-to-source capacitance C gs of the pullup transistor is used to self-bootstrap the input data signal. A pass n-channel transistor is connected between the input data signal, and the gate of the pullup transistor, and is biased on a gate terminal thereof by a charge pump having a voltage magnitude one device threshold higher than the device operating rail V cc . The pass transistor, so biased, permits the input data signal, which may have a magnitude of V cc , to charge C gs . An over-voltage can be developed on the gate of the pullup transistor by the self-bootstrapping effect of C gs . The pass transistor, in addition, so biased, prevents such over-voltage on the pullup transistors gate from being shorted to V cc through a driving device. The output buffer also includes a p-channel transistor having source and drain terminals defining a channel that is connected between another pumped voltage rail, and the gate of the pullup transistor. This p-channel transistor is activated when the output on the pad is desired to be a logic one, and operates to replenish any charge lost on the bootstrap capacitance due to leakage on the gate of the pullup transistor, or from leakage on the drain of the pass transistor. A second capacitor, similar in size to the pass transistor capacitance, is connected between the gate of the pass transistor, and the gate of a pulldown n-channel transistor, and operates to equalize and reduce the effect of transition changes in the input data signal.

Selectively grown vertical Si-p MOS transistor with short channel lengths

Abstract: Vertical p-MOS transistors with channel lengths of ~130 nm have been fabricated using selective LPCVD epitaxy for the definition of the channel region, instead of fine line lithography. Owing to self-aligned facet growth the channel region and the volume diode which limited the parasitic bipolar transistor can be designed more independently. Thus a short-channel p-MOS transistor with a high breakthrough voltage, an ideal subthreshold behaviour and a high transconductance was fabricated.

Non-volatile programmable memory cell for programmable logic array

Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.